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| latticeecp/ec family data sheet version 01.3
www.latticesemi.com 1-1 introduction_01.2 november 2004 preliminary data sheet ? 2004 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci cations and information herein are subject to change without notice. features ? ? ? ? ? ? ? ? ? ash interface ? 1.2v power supply ta b le 1-1. latticeecp/ec family selection guide device lfec1 lfec3 lfec6/ lfecp6 lfec10/ lfecp10 lfec15/ lfecp15 lfec20/ lfecp20 lfec33/ lfecp33 lfec40/ lfecp40 pfu/pff rows 12 16 24 32 40 44 64 64 pfu/pff columns 16 24 32 40 48 56 64 80 pfus/pffs 192 384 768 1280 1920 2464 4096 5120 luts (k) 1.5 3.1 6.1 10.2 15.4 19.7 32.8 41.0 distributed ram (kbits) 6 12 25 41 61 79 131 164 ebr sram (kbits) 18 55 92 277 350 424 535 645 ebr sram blocks 2 6 10 30 38 46 58 70 sysdsp blocks 1 ?? 4567810 18x18 multipliers 1 ??16 20 24 28 32 40 v cc v oltage (v) 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 number of plls 22244444 pa ck ag es and i/o combinations: 100-pin tqfp (14 x 14 mm) 67 67 144-pin tqfp (20 x 20 mm) 97 97 97 208-pin pqfp (28 x 28 mm) 112 145 147 147 256-ball fpbga (17 x 17 mm) 160 195 195 195 484-ball fpbga (23 x 23 mm) 224 288 352 360 360 672-ball fpbga (27 x 27 mm) 400 496 496 900-ball fpbga (31 x 31 mm) 576 1. latticeecp devices only. latticeecp/ec family data sheet introduction 1-2 introduction lattice semiconductor latticeecp/ec family data sheet introduction the latticeecp/ec family of fpga devices has been optimized to deliver mainstream fpga features at low cost. f or maximum performance and value, the latticeecp (ec onomy p lus) fpga concept combines an ef t cient fpga f abric with high-speed dedicated functions. lattice?s t rst family to implement this approach is the latticeecp-dsp (ec onomy p lus dsp ) family, providing dedicated high-performance dsp blocks on-chip. the latticeec? (ec on- omy) family supports all the general purpose features of latticeecp devices without dedicated function blocks to achieve lower cost solutions. the latticeecp/ec fpga fabric, which was designed from the outset with low cost in mind, contains all the critical fpga elements: lut-based logic, distributed and embedded memory, plls and support for mainstream i/os. dedicated ddr memory interface logic is also included to support this memory that is becoming increasingly prev- alent in cost-sensitive applications. the isplever ? design tool from lattice allows large complex designs to be ef t ciently implemented using the latti- ceecp/ec family of fpga devices. synthesis library support for latticeecp/ec is available for popular logic syn- thesis tools. the isplever tool uses the synthesis tool output along with the constraints from its ? oor planning tools to place and route the design in the latticeecp/ec device. the isplever tool extracts the timing from the routing and back-annotates it into the design for timing veri t cation. lattice provides many pre-designed ip (intellectual property) isplevercore? modules for the latticeecp/ec f amily. by using these ips as standardized blocks, designers are free to concentrate on the unique aspects of their design, increasing their productivity. www.latticesemi.com 2-1 architecture_01.3 november 2004 preliminary data sheet ? 2004 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci t cations and information herein are subject to change without notice. architecture overview the latticeecp?-dsp and latticeec? architectures contain an array of logic blocks surrounded by programma- b le i/o cells (pic). interspersed between the rows of logic blocks are rows of sysmem embedded block ram (ebr) as shown in figures 2-1 and 2-2. in addition, latticeecp-dsp supports an additional row of dsp blocks as shown in figure 2-2. there are two kinds of logic blocks, the programmable functional unit (pfu) and programmable functional unit without ram/rom (pff). the pfu contains the building blocks for logic, arithmetic, ram, rom and register func- tions. the pff block contains building blocks for logic, arithmetic and rom functions. both pfu and pff blocks are optimized for ? e xibility allowing complex designs to be implemented quickly and ef t ciently. logic blocks are arranged in a two-dimensional array. only one type of block is used per row. the pfu blocks are used on the out- side rows. the rest of the core consists of rows of pff blocks interspersed with rows of pfu blocks. for every three rows of pff blocks there is a row of pfu blocks. each pic block encompasses two pios (pio pairs) with their respective sysio interfaces. pio pairs on the left and r ight edges of the device can be con t gured as lvds transmit/receive pairs. sysmem ebrs are large dedicated fast memory blocks. they can be con t gured as ram or rom. the pfu, pff, pic and ebr blocks are arranged in a two-dimensional grid with rows and columns as shown in figure 2-1. the blocks are connected with many vertical and horizontal routing channel resources. the place and route software tool automatically allocates these routing resources. at the end of the rows containing the sysmem blocks are the sysclock phase locked loop (pll) blocks. these plls have multiply, divide and phase shifting capability; they are used to manage the phase relationship of the clocks. the latticeecp/ec architecture provides up to four plls per device. every device in the family has a jtag port with internal logic analyzer (isptracy) capability. the sysconfig? port which allows for serial or parallel device con t guration. the latticeecp/ec devices use 1.2v as their core volt- age. latticeecp/ec family data sheet architecture 2-2 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-1. simplited block diagram, latticeecp/ec device (top level) figure 2-2. simplited block diagram, latticeecp-dsp device (top level) programmable i/o cell (pic) includes sysio interface sysconfig programming po rt (includes dedicated and dual use pins) programmable functional unit (pfu) sysclock pll pff (pfu without ram) jtag port sysmem embedded block ram (ebr) programmable i/o cell (pic) includes sysio interface sysconfig programming po rt (includes dedicated and dual use pins) programmable functional unit (pfu) sysdsp block sysclock pll pff (fast pfu without ram/rom) jtag port sysmem embedded block ram (ebr) 2-3 architecture lattice semiconductor latticeecp/ec family data sheet pfu and pff blocks the core of the latticeecp/ec devices consists of pfu and pff blocks. the pfus can be programmed to perform logic, arithmetic, distributed ram and distributed rom functions. pff blocks can be programmed to perform logic, arithmetic and rom functions. except where necessary, the remainder of the data sheet will use the term pfu to refer to both pfu and pff blocks. each pfu block consists of four interconnected slices, numbered 0-3 as shown in figure 2-3. all the interconnec- tions to and from pfu blocks are from routing. there are 53 inputs and 25 outputs associated with each pfu block. figure 2-3. pfu diagram slice each slice contains two lut4 lookup tables feeding two registers (programmed to be in ff or latch mode), and some associated logic that allows the luts to be combined to perform functions such as lut5, lut6, lut7 and lut8. there is control logic to perform set/reset functions (programmable as synchronous/asynchronous), clock select, chip-select and wider ram/rom functions. figure 2-4 shows an overview of the internal logic of the slice. the registers in the slice can be con t gured for positive/negative and edge/level clocks. there are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or pfu). there are 7 outputs: 6 to routing and one to carry-chain (to adjacent pfu). table 2-1 lists the signals associated with each slice. slice 0 lut4 & carry lut4 & carry ff/ latch d ff/ latch d slice 1 lut4 & carry lut4 & carry slice 2 lut4 & carry lut4 & carry from routing to routing slice 3 lut4 & carry lut4 & carry ff/ latch d ff/ latch d ff/ latch d ff/ latch d ff/ latch d ff/ latch d 2-4 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-4. slice diagram ta b le 2-1. slice signal descriptions function type signal names description input data signal a0, b0, c0, d0 inputs to lut4 input data signal a1, b1, c1, d1 inputs to lut4 input multi-purpose m0 multipurpose input input multi-purpose m1 multipurpose input input control signal ce clock enable input control signal lsr local set/reset input control signal clk system clock input inter-pfu signal fcin fast carry in 1 output data signals f0, f1 lut4 output register bypass signals output data signals q0, q1 register outputs output data signals ofx0 output of a lut5 mux output data signals ofx1 output of a lut6, lut7, lut8 2 mux depending on the slice output inter-pfu signal fco for the right most pfu the fast carry chain output 1 1. see figure 2-3 for connection details. 2. requires two pfus. lut4 & carry lut4 & carry slice a0 b0 c0 d0 ff/ latch ofx0 f0 q0 a1 b1 c1 d1 ci ci co co f sum ce clk lsr ff/ latch ofx1 f1 q1 f sum d d m1 to / from different slice / pfu to / from different slice / pfu lut expansion mux m0 ofx0 from routing to routing control signals selected and inverted per slice in routing interslice signals are not shown 2-5 architecture lattice semiconductor latticeecp/ec family data sheet modes of operation each slice is capable of four modes of operation: logic, ripple, ram and rom. the slice in the pff is capable of all modes except ram. table 2-2 lists the modes and the capability of the slice blocks. ta b le 2-2. slice modes logic mode: in this mode, the luts in each slice are con t gured as 4-input combinatorial lookup tables. a lut4 can have 16 possible input combinations. any logic function with four inputs can be generated by programming this lookup table. since there are two lut4s per slice, a lut5 can be constructed within one slice. larger lookup tables such as lut6, lut7 and lut8 can be constructed by concatenating other slices. ripple mode: ripple mode allows the ef t cient implementation of small arithmetic functions. in ripple mode, the fol- lowing functions can be implemented by each slice: ? addition 2-bit ? subtraction 2-bit ? add/subtract 2-bit using dynamic control ? up counter 2-bit ?d o wn counter 2-bit ? ripple mode multiplier building block ? comparator functions of a and b inputs -a greater-than-or-equal-to b -a not-equal-to b -a less-than-or-equal-to b tw o additional signals: carry generate and carry propagate are generated per slice in this mode, allowing fast arithmetic functions to be constructed by concatenating slices. ram mode: in this mode, distributed ram can be constructed using each lut block as a 16x1-bit memory. through the combination of luts and slices, a variety of different memories can be constructed. the lattice design tools support the creation of a variety of different size memories. where appropriate, the soft- w are will construct these using distributed memory primitives that represent the capabilities of the pfu. table 2-3 shows the number of slices required to implement different distributed ram primitives. figure 2-5 shows the dis- tributed memory primitive block diagrams. dual port memories involve the pairing of two slices, one slice functions as the read-write port. the other companion slice supports the read-only port. for more information on using ram in latticeecp/ec devices, please see details of additional technical documentation at the end of this data sheet. ta b le 2-3. number of slices required for implementing distributed ram logic ripple ram rom pfu slice lut 4x2 or lut 5x1 2-bit arithmetic unit spr16x2 rom16x1 x 2 pff slice lut 4x2 or lut 5x1 2-bit arithmetic unit n/a rom16x1 x 2 spr16x2 dpr16x2 number of slices 1 2 note: spr = single port ram, dpr = dual port ram 2-6 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-5. distributed memory primitives r om mode: the rom mode uses the same principal as the ram modes, but without the write port. pre-loading is accomplished through the programming interface during con t guration. pfu modes of operation slices can be combined within a pfu to form larger functions. table 2-4 tabulates these modes and documents the functionality possible at the pfu level. ta b le 2-4. pfu modes of operation logic ripple ram 1 rom lut 4x8 or mux 2x1 x 8 2-bit add x 4 spr16x2 x 4 dpr16x2 x 2 r om16x1 x 8 lut 5x4 or mux 4x1 x 4 2-bit sub x 4 spr16x4 x 2 dpr16x4 x 1 r om16x2 x 4 lut 6x 2 or mux 8x1 x 2 2-bit counter x 4 spr16x8 x 1 rom16x4 x 2 lut 7x1 or mux 16x1 x 1 2-bit comp x 4 rom16x8 x 1 1. these modes are not available in pff blocks do1 do0 di0 di1 ad0 ad1 ad2 ad3 wre ck do0 ad0 ad1 ad2 ad3 dpr16x2 spr16x2 r om16x1 rdo1 rdo0 di0 di1 wck wre wdo1 wdo0 wad0 w ad1 wad2 wad3 rad0 rad1 rad2 rad3 2-7 architecture lattice semiconductor latticeecp/ec family data sheet routing there are many resources provided in the latticeecp/ec devices to route signals individually or as busses with related control signals. the routing resources consist of switching circuitry, buffers and metal interconnect (routing) segments. the inter-pfu connections are made with x1 (spans two pfu), x2 (spans three pfu) and x6 (spans seven pfu). the x1 and x2 connections provide fast and ef t cient connections in horizontal and vertical directions. the x2 and x6 resources are buffered allowing both short and long connections routing between pfus. the isplever design tool takes the output of the synthesis tool and places and routes the design. generally, the place and route tool is completely automatic, although an interactive routing editor is available to optimize the design. clock distribution network the clock inputs are selected from external i/o, the sysclock? plls or routing. these clock inputs are fed through the chip via a clock distribution system. primary clock sources latticeecp/ec devices derive clocks from three primary sources: pll outputs, dedicated clock inputs and routing. latticeecp/ec devices have two to four sysclock plls, located on the left and right sides of the device. there are four dedicated clock inputs, one on each side of the device. figure 2-6 shows the 20 primary clock sources. figure 2-6. primary clock sources fr om routing clock input from routing pll input clock input pll input pll input clock input pll input fr om routing clock input from routing pll pll pll pll 20 primary clock sources to quadrant clock selection note: smaller devices have two plls. 2-8 architecture lattice semiconductor latticeecp/ec family data sheet secondary clock sources latticeecp/ec devices have four secondary clock resources per quadrant. the secondary clock branches are tapped at every pfu. these secondary clock networks can also be used for controls and high fanout data. these secondary clocks are derived from four clock input pads and 16 routing signals as shown in figure 2-7. figure 2-7. secondary clock sources clock routing the clock routing structure in latticeecp/ec devices consists of four primary clock lines and a secondary clock network per quadrant. the primary clocks are generated from muxs located in each quadrant. figure 2-8 shows this clock routing. the four secondary clocks are generated from muxs located in each quadrant as shown in figure 2-9. each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in figure 2-10. 20 secondary clock sources to quadrant clock selection f rom routing f rom routing f rom routing f rom routing f rom routing f rom routing f rom routing f rom routing f rom routing f rom routing f rom routing f rom routing f rom routing f rom routing f rom routing f rom routing 2-9 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-8. per quadrant primary clock selection figure 2-9. per quadrant secondary clock selection figure 2-10. slice clock selection sysclock phase locked loops (plls) the pll clock input, from pin or routing, feeds into an input clock divider. there are three sources of feedback sig- nal to the feedback divider: from the clkop, from the clock net, or from an external pin. there is a pll_lock sig- nal to indicate that vco has locked on to the input clock signal. figure 2-11 shows the sysclock pll diagram. the setup and hold times of the device can be improved by programming a delay in the feedback or input path of the pll which will advance or delay the output clock with reference to the input clock. this delay can be either pro- gr ammed during con t guration or can be adjusted dynamically. in dynamic mode, the pll may lose lock after 4 primary clocks (clk0, clk1, clk2, clk3) per quadrant 20 primary clock sources: 12 plls + 4 pios + 4 routing 1 dcs dcs 1. smaller devices have fewer pll related lines. 4 secondary clocks per quadrant 20 secondary clock feedlines : 4 clock input pads + 16 routing signals primary clock secondary clock routing clock to slice gnd 4 3 2-10 architecture lattice semiconductor latticeecp/ec family data sheet adjustment and not relock until the t lock parameter has been satis t ed. additionally, the phase and duty cycle block allows the user to adjust the phase and duty cycle of the clkos output. the sysclock plls provide the ability to synthesize clock frequencies. each pll has four dividers associated with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. the input clock divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. the post scalar divider allows the vco to operate at higher frequencies than the clock output, thereby increasing the fre- quency range. the secondary divider is used to derive lower frequency outputs. figure 2-11. pll diagram figure 2-12 shows the available macros for the pll. table 2-5 provides signal description of the pll block. figure 2-12. pll primitive vco clkos clkok lock rst clkfb (from clkop, clock net or e xternal pin) dynamic delay adjustment input clock divider (clki) feedback divider (clkfb) po st scalar divider (clkop) phase/duty select secondary clock divider (clkok) delay adjust v oltage controlled oscillator clki (from routing or e xternal pin) clkop epllb clkop clki clkfb lock ehxpllb clkos clki clkfb clkok lock rst clkop ddaizr ddailag dda mode ddaidel[2:0] ddaozr ddaolag ddaodel[2:0] 2-11 architecture lattice semiconductor latticeecp/ec family data sheet ta b le 2-5. pll signal descriptions f or more information on the pll, please see details of additional technical documentation at the end of this data sheet. dynamic clock select (dcs) the dcs is a global clock buffer with smart multiplexer functions. it takes two independent input clock sources and outputs a clock signal without any glitches or runt pulses. this is achieved irrespective of where the select signal is toggled. there are eight dcs blocks per device, located in pairs at the center of each side. figure 2-13 illustrates the dcs block macro. figure 2-13. dcs block primitive figure 2-14 shows timing waveforms of the default dcs operating mode. the dcs block can be programmed to other modes. for more information on the dcs, please see details of additional technical documentation at the end of this data sheet. signal i/o description clki i clock input from external pin or routing clkfb i pll feedback input from clkop, clocknet, or external pin rst i ?1? to reset pll clkos o pll output clock to clock tree (phase shifted/duty cycle changed) clkop o pll output clock to clock tree (no phase shift) clkok o pll output to clock tree through secondary clock divider lock o ?1? indicates pll lock to clki ddamode i dynamic delay enable. ?1?: pin control (dynamic), ?0?: fuse control (static) ddaizr i dynamic delay zero. ?1?: delay = 0, ?0?: delay = on ddailag i dynamic delay lag/lead. ?1?: lead, ?0?: lag ddaidel[2:0] i dynamic delay input ddaozr o dynamic delay zero output ddaolag o dynamic delay lag/lead output ddaodel[2:0] o dynamic delay output dcs clk0 dcsout clk1 sel 2-12 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-14. dcs waveforms sysmem memory the latticeecp/ec family of devices contain a number of sysmem embedded block ram (ebr). the ebr con- sists of a 9-kbit ram, with dedicated input and output registers. sysmem memory block the sysmem block can implement single port, dual port or pseudo dual port memories. each block can be used in a variety of depths and widths as shown in table 2-6. ta b le 2-6. sysmem block contgurations bus size matching all of the multi-port memory modes support different widths on each of the ports. the ram bits are mapped lsb w ord 0 to msb word 0, lsb word 1 to msb word 1 and so on. although the word size and number of words for each port varies, this mapping scheme applies to each port. ram initialization and rom operation if desired, the contents of the ram can be pre-loaded during device con t guration. by preloading the ram block during the chip con t guration cycle and disabling the write controls, the sysmem block can also be utilized as a r om. memory mode con gurations single port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 tr ue dual port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 pseudo dual port 8,192 x 1 4,096 x 2 2,048 x 4 1,024 x 9 512 x 18 256 x 36 clk0 sel dcsout clk1 2-13 architecture lattice semiconductor latticeecp/ec family data sheet memory cascading larger and deeper blocks of rams can be created using ebr sysmem blocks. typically, the lattice design tools cascade memory transparently, based on speci t c design inputs. single, dual and pseudo-dual port modes figure 2-15 shows the four basic memory con t gurations and their input/output names. in all the sysmem ram modes the input data and address for the ports are registered at the input of the memory array. the output data of the memory is optionally registered at the output. figure 2-15. sysmem ebr primitives the ebr memory supports three forms of write behavior for single port or dual port operation: 1. normal ? data on the output appears only during read cycle. during a write cycle, the data (at the current address) does not appear on the output. 2. write through ? a copy of the input data appears at the output of the same port, during a write cycle. 3. read-before-write ? when new data is being written, the old content of the address appears at the output. memory core reset the memory array in the ebr utilizes latches at the a and b output ports. these latches can be reset asynchro- nously or synchronously. rsta and rstb are local signals, which reset the output latches associated with port a and port b respectively. the global reset (gsrn) signal resets both ports. the output data latches and associated resets for both ports are as shown in figure 2-16. ebr ad[12:0] di[35:0] clk ce rst we cs[2:0] do[35:0] single port ram ebr t rue dual port ram pseudo-dual port ram rom ad[12:0] clk ce do[35:0] rst cs[2:0] ebr ebr ada[12:0] dia[17:0] clka cea rsta wea csa[2:0] doa[17:0] adb[12:0] dib[17:0] clkb ceb rstb web csb[2:0] dob[17:0] adw[12:0] di[35:0] clkw cew adr[12:0] do[35:0] cer clkr we rst cs[2:0] 2-14 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-16. memory core reset f or further information on sysmem ebr block, please see the details of additional technical documentation at the end of this data sheet. sysdsp block the latticeecp-dsp family provides a sysdsp block making it ideally suited for low cost, high performance digital signal processing (dsp) applications. typical functions used in these applications are finite impulse response (fir) t lters; fast fourier transforms (fft) functions, correlators, reed-solomon/turbo/convolution encoders and decoders. these complex signal processing functions use similar building blocks such as multiply-adders and mul- tiply-accumulators. sysdsp block approach compare to general dsp conventional general-purpose dsp chips typically contain one to four (multiply and accumulate) mac units with t x ed data-width multipliers; this leads to limited parallelism and limited throughput. their throughput is increased by higher clock speeds. the latticeecp, on the other hand, has many dsp blocks that support different data-widths. this allows the designer to use highly parallel implementations of dsp functions. the designer can optimize the dsp performance vs. area by choosing appropriate level of parallelism. figure 2-17 compares the serial and the parallel implementations. q set d l clr output data latches memory core port a[17:0] q set d port b[17:0] rstb gsrn programmable disable rsta l clr 2-15 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-17. comparison of general dsp and latticeecp-dsp approaches sysdsp block capabilities the sysdsp block in the latticeecp-dsp family supports four functional elements in three 9, 18 and 36 data path widths. the user selects a function element for a dsp block and then selects the width and type (signed/unsigned) of its operands. the operands in the latticeecp-dsp family sysdsp blocks can be either signed or unsigned but not mixed within a function element. similarly, the operand widths cannot be mixed within a block. the resources in each sysdsp block can be con t gured to support the following four elements: ? mult (multiply) ?m ac (multiply, accumulate) ? multadd (multiply, addition/subtraction) ? multaddsum (multiply, addition/subtraction, accumulate) the number of elements available in each block depends in the width selected from the three available options x9, x18, and x36. a number of these elements are concatenated for highly parallel implementations of dsp functions. ta b le 2-1 shows the capabilities of the block. ta b le 2-7. maximum number of elements in a block some options are available in four elements. the input register in all the elements can be directly loaded or can be loaded as shift register from previous operand registers. in addition by selecting ?dynamic operation? in the ?signed/ unsigned? options the operands can be switched between signed and unsigned on every cycle. similarly by select- ing ?dynamic operation? in the ?add/sub? option the accumulator can be switched between addition and subtraction on every cycle. width of multiply x9 x18 x36 mult 8 4 1 mac 4 2 ? multadd 4 2 ? multaddsum 2 1 ? multiplier 0 operand a operand b operand a operand b operand a operand b multiplier 1 multiplier (k-1) accumulator output m/k loops single multiplier x xx x operand a accumulator operand b m loops function implemented in general purpose dsp function implemented in latticeecp " " 2-16 architecture lattice semiconductor latticeecp/ec family data sheet mult sysdsp element this multiplier element implements a multiply with no addition or accumulator nodes. the two operands, a and b, are multiplied and the result is available at the output. the user can enable the input/output and pipeline registers. figure 2-18 shows the mult sysdsp element. figure 2-18. mult sysdsp element mac sysdsp element in this case the two operands, a and b, are multiplied and the result is added with the previous accumulated value. this accumulated value is available at the output. the user can enable the input and pipeline registers but the out- put register is always enabled. the output register is used to store the accumulated value. a registered over ? ow signal is also available. the over ? ow conditions are provided later in this document. figure 2-19 shows the mac sysdsp element. figure 2-19. mac sysdsp element multiplier x n m m n m n m n n m m+n m+n (default) clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) pipeline register input register multiplier multiplicand signed shift register a in shift register b in shift register a out shift register b out output input data register a input data register b output register to multiplier multiplier x n m m+n (default) m+n+16 bits (default) m+n+16 bits (default) input data register b input data register a m n n n m n n m overflow register output register accumulator multiplier multiplicand signedab shift register a in shift register b in shift register a out shift register b out output addn accumsload pipeline register clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) input register pipeline register input register pipeline register input register pipeline register to accumulator to accumulator to accumulator overflow signal 2-17 architecture lattice semiconductor latticeecp/ec family data sheet multadd sysdsp element in this case, the operands a0 and b0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands a1 and a2. the user can enable the input, output and pipeline registers. figure 2-20 shows the multadd sysdsp element. figure 2-20. multadd multaddsum sysdsp element in this case, the operands a0 and b0 are multiplied and the result is added/subtracted with the result of the multi- plier operation of operands a1 and b1. additionally the operands a2 and b2 are multiplied and the result is added/ subtracted with the result of the multiplier operation of operands a3 and b3. the result of both addition/subtraction are added in a summation block. the user can enable the input, output and pipeline registers. figure 2-21 shows the multaddsum sysdsp element. multiplier multiplier add/sub pipe reg pipe reg n m m n m n m n n m m+n (default) m+n+1 (default) m+n+1 (default) m+n (default) x x n m m n m n n m multiplier b0 multiplicand a0 multiplier b1 multiplicand a1 signed shift register a in shift register b in shift register a out shift register b out output addn pipeline register clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) input register pipeline register input register pipeline register pipeline register input data register a input data register a input data register b input data register b output register to add/sub to add/sub 2-18 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-21. multaddsum clock, clock enable and reset resources global clock, clock enable and reset signals from routing are available to every dsp block. four clock, reset and clock enable signals are selected for the sysdsp block. from four clock sources (clk0, clk1, clk2, clk3) one clock is selected for each input register, pipeline register and output register. similarly clock enable (ce) and reset (rst) are selected from their four respective sources (ce0, ce1, ce2, ce3 and rst0, rst1, rst2, rst3) at each input register, pipeline register and output register. signed and unsigned with different widths the dsp block supports different widths of signed and unsigned multipliers besides x9, x18 and x36 widths. for unsigned operands, unused upper data bits should be t lled to create a valid x9, x18 or x36 operand. for signed two?s complement operands, sign extension of the most signi t cant bit should be performed until x9, x18 or x36 width is reached. table 2-8 provides an example of this. multiplier add/sub0 x n m m+n (default) m+n (default) m+n+1 m+n+2 m+n+2 m+n+1 m+n (default) m+n (default) m n m n m n n m x n n m n n m multiplier multiplier multiplier add/sub1 x n m m n m n m n n m x n m m n m n n m sum multiplier b0 multiplicand a0 multiplier b1 multiplicand a1 multiplier b2 multiplicand a2 multiplier b3 multiplicand a3 signed shift register b in output addn0 pipeline register clk (clk0,clk1,clk2,clk3) ce (ce0,ce1,ce2,ce3) rst(rst0,rst1,rst2,rst3) input register pipeline register input register to add/sub0 to add/sub0, add/sub1 pipeline register pipeline register input register to add/sub1 addn1 pipeline register pipeline register pipeline register shift register a in shift register b out shift register a out input data register a input data register a input data register a input data register a input data register b input data register b input data register b input data register b output register 2-19 architecture lattice semiconductor latticeecp/ec family data sheet ta b le 2-8. an example of sign extension o verflow flag from mac the sysdsp block provides an over ? ow output to indicate that the accumulator has over ? ow ed. when two unsigned numbers are added and the result is a smaller number then accumulator roll over is said to occur and over ? ow signal is indicated. when two positive numbers are added with a negative sum and when two negative n umbers are added with a positive sum, then the accumulator ?roll-over? is said to have occurred and an over ? ow signal is indicated. note when over ? ow occurs the over ? ow ? ag is present for only one cycle. by counting these over ? ow pulses in fpga logic, larger accumulators can be constructed. the conditions over ? ow signal for signed and unsigned operands are listed in figure 2-22. figure 2-22. accumulator over?ow/under?ow conditions isplever module manager the user can access the sysdsp block via the isplever module manager, which has options to con t gure each dsp module (or group of modules) or through direct hdl instantiation. additionally lattice has partnered math- wo r ks to support instantiation in the simulink tool, which is a graphical simulation environment. simulink works with isplever and dramatically shortens the dsp design cycle in lattice fpgas. number unsigned unsigned 9-bit unsigned 18-bit signed tw o?s complement signed 9-bits tw o?s complement signed 18-bits +5 0101 000000101 000000000000000101 0101 000000101 000000000000000101 -6 0110 000000110 000000000000000110 1010 111111010 111111111111111010 000000000 000000001 000000010 000000011 111111101 111111110 111111111 overflow signal is generated for one cycle when this boundary is crossed 0 +1 +2 +3 -3 -2 -1 unsigned operation signed operation 0101111111 0101111110 0101111101 0101111100 1010000010 1010000001 1010000000 255 254 253 252 254 255 256 000000000 000000001 000000010 000000011 111111101 111111110 111111111 carry signal is generated for one cycle when this boundary is crossed 0 1 2 3 509 510 511 0101111111 0101111110 0101111101 0101111100 1010000010 1010000001 1010000000 255 254 253 252 258 257 256 2-20 architecture lattice semiconductor latticeecp/ec family data sheet optimized dsp functions lattice provides a library of optimized dsp ip functions. some of the ips planned for latticeecp dsp are: bit cor- relators, fast fourier transform, finite impulse response (fir) filter, reed-solomon encoder/ decoder, turbo encoder/decoders and convolutional encoder/decoder. please contact lattice to obtain the latest list of available dsp ips. resources available in the latticeecp family ta b le 2-9 shows the maximum number of multipliers for each member of the latticeecp family. table 2-10 shows the maximum available ebr ram blocks in each of the latticeecp family. ebr blocks, together with distributed ram can be used to store variables locally for the fast dsp operations. ta b le 2-9. number of dsp blocks in latticeecp family ta b le 2-10. embedded sram in latticeecp family dsp performance of the latticeecp family ta b le 2-11 lists the maximum performance in millions of mac operations per second (mmac) for each member of the latticeecp family. ta b le 2-11. dsp block performance of latticeecp family f or further information on the sysdsp block, please see details of additional technical information at the end of this data sheet. device dsp block 9x9 multiplier 18x18 multiplier 36x36 multiplier lfecp6 4 32 16 4 lfecp10 5 40 20 5 lfecp15 6 48 24 6 lfecp20 7 56 28 7 lfecp33 8 64 32 8 lfecp40 10 80 40 10 device ebr sram block t otal ebr sram (kbits) lfecp6 10 92 lfecp10 30 276 lfecp15 38 350 lfecp20 46 424 lfecp33 58 535 lfecp40 70 645 device dsp block dsp performance mmac lfecp6 4 3680 lfecp10 5 4600 lfecp15 6 5520 lfecp20 7 6440 lfecp33 8 7360 lfecp40 10 9200 2-21 architecture lattice semiconductor latticeecp/ec family data sheet programmable i/o cells (pic) each pic contains two pios connected to their respective sysio buffers which are then connected to the pads as shown in figure 2-23. the pio block supplies the output data (do) and the tri-state control signal (to) to sysio b uffer, and receives input from the buffer. figure 2-23. pic diagram tw o adjacent pios can be joined to provide a differential i/o pair (labeled as ?t? and ?c?) as shown in figure 2-24. the pad labels ?t? and ?c? distinguish the two pios. only the pio pairs on the left and right edges of the device can be con t gured as lvds transmit/receive pairs. one of every 16 pios contains a delay element to facilitate the generation of dqs signals. the dqs signal feeds the dqs bus which spans the set of 16 pios. figure 2-24 shows the assignment of dqs pins in each set of 16 pios. the exact dqs pins are shown in a dual function in the logic signal connections table at the end of this data sheet. additional detail is provided in the signal descriptions table at the end of this data sheet. the dqs signal from the bus is used to strobe the ddr data from the memory into input register blocks. this interface is designed f or memories that support one dqs strobe per eight bits of data. pio b pada "t" p adb "c" opos0 oneg0 opos1 oneg1 td inck indd inff ipos0 ipos1 clk ce lsr gsrn pio a sysio buffer dqs ddrclkpol iold0 iolt0 d0 ddrclk di ipos1 ipos0 inck indd inff d0 d1 td d1 output register block (2 flip flops) t ristate register block (2 flip flops) ddrclk input register block (5 flip flops) clko clki ceo cei control muxes lsr gsr 2-22 architecture lattice semiconductor latticeecp/ec family data sheet ta b le 2-12. pio signal list figure 2-24. dqs routing pio the pio contains four blocks: an input register block, output register block, tristate register block and a control logic b lock. these blocks contain registers for both single data rate (sdr) and double data rate (ddr) operation along with the necessary clock and selection logic. programmable delay lines used to shift incoming clock and data sig- nals are also included in these blocks. name type description ce0, ce1 control from the core clock enables for input and output block ffs. clk0, clk1 control from the core system clocks for input and output blocks. lsr control from the core local set/reset. gsrn control from routing global set/reset (active low). inck input to the core input to primary clock network or pll reference inputs. dqs input to pio dqs signal from logic (routing) to pio. indd input to the core unregistered data input to core. inff input to the core registered input on positive edge of the clock (clk0). ipos0, ipos1 input to the core ddrx registered inputs to the core. oneg0 control from the core output signals from the core for sdr and ddr operation. opos0, control from the core output signals from the core for ddr operation opos1 oneg1 tristate control from the core signals to tristate register block for ddr operation. td tristate control from the core tristate signal from the core used in sdr operation. ddrclkpol control from clock polarity bus controls the polarity of the clock (clk0) that feed the ddr input block. pio a pio b pa da "t" pa d b "c" pio b pio a pio b pio a assigned dqs pin dqs sysio buffer lv d s p air pa da "t" pa d b "c" lv d s p air pa da "t" pa d b "c" lv d s pair pio a pio b pa da "t" pa d b "c" lv d s p air pio a pio b pa da "t" pa d b "c" lv d s p air pio a pio b pa da "t" pa d b "c" lv d s p air pio a pio b pa da "t" pa d b "c" lv d s pair pio a pio b pa da "t" pa d b "c" lv d s pair delay 2-23 architecture lattice semiconductor latticeecp/ec family data sheet input register block the input register block contains delay elements and registers that can be used to condition signals before they are passed to the device core. figure 2-25 shows the diagram of the input register block. input signals are fed from the sysio buffer to the input register block (as signal di). if desired the input signal can b ypass the register and delay elements and be used directly as a combinatorial signal (indd), a clock (inck) and in selected blocks the input to the dqs delay block. if one of the bypass options is not chosen, the signal t rst passes through an optional delay block. this delay, if selected, reduces input-register hold-time requirement when using a global clock. the input block allows two modes of operation. in the single data rate (sdr) the data is registered, by one of the registers in the single data rate sync register block, with the system clock. in the ddr mode two registers are used to sample the data on the positive and negative edges of the dqs signal creating two data streams, d0 and d2. these two data streams are synchronized with the system clock before entering the core. further discussion on this topic is in the ddr memory section of this data sheet. figure 2-26 shows the input register waveforms for ddr operation and figure 2-27 shows the design tool primi- tives. the sdr/sync registers have reset and clock enable available. the signal ddrclkpol controls the polarity of the clock used in the synchronization registers. it ensures ade- quate timing when data is transferred from the dqs to system clock domain. for further discussion on this topic, see the ddr memory section of this data sheet. figure 2-25. input register diagram d q d q d q d-type fixed delay to routing di (from sysio buffer) dqs delayed (from dqs bus) clk0 (from routing) ddrclkpol (from ddr po larity control bus) inck indd delay block ddr registers d-type d-type d q d q d-type /latch /latch d-type ipos0 ipos1 sdr & sync registers d0 d2 d1 2-24 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-26. input register ddr waveforms figure 2-27. inddrxb primitive output register block the output register block provides the ability to register signals from the core of the device before they are passed to the sysio buffers. the block contains a register for sdr operation that is combined with an additional latch for ddr operation. figure 2-28 shows the diagram of the output register block. in sdr mode, oneg0 feeds one of the ? ip- ? ops that then feeds the output. the ? ip- ? op can be con t gured a d- type or latch. in ddr mode, oneg0 is fed into one register on the positive edge of the clock and opos0 is latched. a multiplexer running off the same clock selects the correct register for feeding to the output (d0). figure 2-29 shows the design tool ddr primitives. the sdr output register has reset and clock enable available. the additional register for ddr operation does not have reset or clock enable available. abcde f bd di (in ddr mode) d0 d2 dqs a c dqs delayed iddrxb lsr qa d eclk qb ddrclkpol sclk ce 2-25 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-28. output register block figure 2-29. oddrxb primitive t ristate register block the tristate register block provides the ability to register tri-state control signals from the core of the device before they are passed to the sysio buffers. the block contains a register for sdr operation and an additional latch for ddr operation. figure 2-30 shows the diagram of the tristate register block. in sdr mode, oneg1 feeds one of the ? ip- ? ops that then feeds the output. the ? ip- ? op can be con t gured a d- type or latch. in ddr mode, oneg1 is fed into one register on the positive edge of the clock and opos1 is latched. a multiplexer running off the same clock selects the correct register for feeding to the output (d0). d q d q d-type oneg0 from routing clk1 programmed control do latch le* *latch is transparent when input is low. opos0 outddn /latch 0 1 0 1 to sysio buffer oddrxb lsr q db clk da 2-26 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-30. tristate register block control logic block the control logic block allows the selection and modi t cation of control signals for use in the pio block. a clock is selected from one of the clock signals provided from the general purpose routing and a dqs signal provided from the programmable dqs pin. the clock can optionally be inverted. the clock enable and local reset signals are selected from the routing and optionally inverted. the global tristate signal is passed through this block. ddr memory support implementing high performance ddr memory interfaces requires dedicated ddr register structures in the input (for read operations) and in the output (for write operations). as indicated in the pio logic section, the ec devices provide this capability. in addition to these registers, the ec devices contain two elements to simplify the design of input structures for read operations: the dqs delay block and polarity control logic. dll calibrated dqs delay block source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at the input register. for most interfaces a pll is used for this adjustment, however in ddr memories the clock (referred to as dqs) is not free running so this approach cannot be used. the dqs delay block provides the required clock alignment for ddr memory interfaces. the dqs signal (selected pios only) feeds from the pad through a dqs delay element to a dedicated dqs rout- ing resource. the dqs signal also feeds polarity control logic which controls the polarity of the clock to the sync registers in the input register blocks. figures 2-31 and 2-32 show how the dqs transition signals are routed to the pios. the temperature, voltage and process variations of the dqs delay block are compensated by a set of calibration (6-bit bus) signals from two dlls on opposite sides of the device. each dll compensates dqs delays in its half of the device as shown in figure 2-32. the dll loop is compensated for temperature, voltage and process variations by the system clock and feedback loop. d le* q d q d-type oneg1 clk1 programmed control to latch *latch is transparent when input is low. opos1 outddn /latch 0 1 0 1 from routing to sysio buffer td 2-27 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-31. dqs local bus. figure 2-32. dll calibration bus and dqs/dqs transition distribution di clki cei pio gsr dqs input register block ( 5 flip flops) to sync. reg. dqs to ddr reg. dqs strobe pa d ddr datain pa d sysio buffer di sysio buffer pio dqsdel p olarity control logic dqs calibration bus from dll delay control bus p olarity control bus dqs bus dll dll po larity control bus dqs bus delay control bus 2-28 architecture lattice semiconductor latticeecp/ec family data sheet p olarity control logic in a typical ddr memory interface design, the phase relation between the incoming delayed dqs strobe and the internal system clock (during the read cycle) is unknown. the latticeecp/ec family contains dedicated circuits to transfer data between these domains. to prevent setup and hold violations at the domain transfer between dqs (delayed) and the system clock a clock polarity selector is used. this changes the edge on which the data is registered in the synchronizing registers in the input register b lock. this requires evaluation at the start of each read cycle for the correct clock polarity. prior to the read operation in ddr memories dqs is in tristate (pulled by termination). the ddr memory device drives dqs low at the start of the preamble state. a dedicated circuit detects this transition. this signal is used to control the polarity of the clock to the synchronizing registers. sysio buffer each i/o is associated with a ? e xible buffer referred to as a sysio buffer. these buffers are arranged around the periphery of the device in eight groups referred to as banks. the sysio buffers allow users to implement the wide va r iety of standards that are found in today?s systems including lvcmos, sstl, hstl, lvds and lvpecl. sysio buffer banks latticeecp/ec devices have eight sysio buffer banks; each is capable of supporting multiple i/o standards. each sysio bank has its own i/o supply voltage (v ccio ), and two voltage references v ref1 and v ref2 resources allow- ing each bank to be completely independent from each other. figure 2-33 shows the eight banks and their associ- ated supplies. in the latticeecp/ec devices, single-ended output buffers and ratioed input buffers (lvttl, lvcmos, pci and pci- x) are powered using v ccio. l vttl, lvcmos33, lvcmos25 and lvcmos12 can also be set as t x ed threshold input independent of v ccio. in addition to the bank v ccio supplies, the latticeecp/ec devices have a v cc core logic power supply, and a v ccaux supply that power all differential and referenced buffers. each bank can support up to two separate vref voltages, vref1 and vref2 that set the threshold for the refer- enced input buffers. in the latticeecp/ec devices, some dedicated i/o pins in a bank can be con t gured to be a reference voltage supply pin. each i/o is individually con t gurable based on the bank?s supply and reference volt- ages. 2-29 architecture lattice semiconductor latticeecp/ec family data sheet figure 2-33. latticeecp/ec banks latticeecp/ec devices contain two types of sysio buffer pairs. 1. t op and bottom sysio buffer pair (single-ended outputs only) the sysio buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers and two sets of single-ended input buffers (both ratioed and referenced). the referenced input buffer can also be con t gured as a differential input. the two pads in the pair are described as ?true? and ?comp?, where the true pad is associated with the positive side of the differential input buffer and the comp (complementary) pad is associated with the negative side of the differential input buffer. only the i/os on the top and bottom banks have pci clamp. 2. left and right sysio buffer pair (differential and single-ended outputs) the sysio buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. the refer- enced input buffer can also be con t gured as a differential input. in these banks the two pads in the pair are described as ?true? and ?comp?, where the true pad is associated with the positive side of the differential i/o, and the comp (complementary) pad is associated with the negative side of the differential i/o. only the left and right banks have lvds differential output drivers. supported standards the latticeecp/ec sysio buffer supports both single-ended and differential standards. single-ended standards can be further subdivided into lvcmos, lvttl and other standards. the buffers support the lvttl, lvcmos 1.2, 1.5, 1.8, 2.5 and 3.3v standards. in the lvcmos and lvttl modes, the buffer has individually con t gurable v ref1(2) gnd bank 2 v ccio2 v ref2(2) v ref1(3) gnd bank 3 v ccio3 v ref2(3) v ref1(7) gnd bank 7 v ccio7 v ref2(7) v ref1(6) gnd note: n and m are the maximum number of i/os per bank. bank 6 v ccio6 v ref2(6) v ref1(5) gnd bank 5 v ccio5 v ref2( 5) v ref1( 4) gnd bank 4 v ccio4 v ref2( 4) v ref1( 0) gnd bank 0 v ccio 0 v ref2( 0) v ref1(1) gnd bank 1 v ccio 1 v ref2 (1) m 2-30 architecture lattice semiconductor latticeecp/ec family data sheet options for drive strength, bus maintenance (weak pull-up, weak pull-down, or a bus-keeper latch) and open drain. other single-ended standards supported include sstl and hstl. differential standards supported include lvds, blvds, lvpecl, rsds, differential sstl and differential hstl. tables 2-13 and 2-14 show the i/o standards (together with their supply and reference voltages) supported by the latticeecp/ec devices. for further informa- tion on utilizing the sysio buffer to support a variety of standards please see the details of additional technical infor- mation at the end of this data sheet. ta b le 2-13. supported input standards input standard v ref (nom.) v ccio 1 (nom.) single ended interfaces l vttl ? ? l vcmos33 2 ?? l vcmos25 2 ?? l vcmos18 ? 1.8 l vcmos15 ? 1.5 l vcmos12 2 ?? pci ? 3.3 hstl18 class i, ii 0.9 ? hstl18 class iii 1.08 ? hstl15 class i 0.75 ? hstl15 class iii 0.9 ? sstl3 class i, ii 1.5 ? sstl2 class i, ii 1.25 ? sstl18 class i 0.9 ? differential interfaces differential sstl18 class i ? ? differential sstl2 class i, ii ? ? differential sstl3 class i, ii ? ? differential hstl15 class i, iii ? ? differential hstl18 class i, ii, iii ? ? l vds, lvpecl, blvds, rsds ? ? 1. when not speci t ed v ccio can be set anywhere in the valid operating range. 2. jtag inputs do not have a t x ed threshold option and always follow v ccj. 2-31 architecture lattice semiconductor latticeecp/ec family data sheet ta b le 2-14. supported output standards hot socketing the latticeecp/ec devices have been carefully designed to ensure predictable behavior during power-up and power-down. power supplies can be sequenced in any order. during power up and power-down sequences, the i/os remain in tristate until the power supply voltage is high enough to ensure reliable operation. in addition, leakage into i/o pins is controlled to within speci t ed limits, this allows for easy integration with the rest of the system. these capabilities make the latticeecp/ec ideal for many multiple power supply and hot-swap applica- tions. recommended power up sequence : as described in the previous paragraph, the supplies can be sequenced in any order. however, once internal power good is achieved (determined by vcc, vccaux, vccio bank 5) the part releases i/os from tri-state and the management of i/os becomes the designers responsibility. to simplify a system design it is therefore recommended that supplies be sequenced vccio, vcc, vccaux. output standard drive v ccio (nom.) single-ended interfaces l vttl 4ma, 8ma, 12ma, 16ma, 20ma 3.3 l vcmos33 4ma, 8ma, 12ma 16ma, 20ma 3.3 l vcmos25 4ma, 8ma, 12ma, 16ma, 20ma 2.5 l vcmos18 4ma, 8ma, 12ma, 16ma 1.8 l vcmos15 4ma, 8ma 1.5 l vcmos12 2ma, 6ma 1.2 l vcmos33, open drain 4ma, 8ma, 12ma 16ma, 20ma ? l vcmos25, open drain 4ma, 8ma, 12ma 16ma, 20ma ? l vcmos18, open drain 4ma, 8ma, 12ma 16ma ? l vcmos15, open drain 4ma, 8ma ? l vcmos12, open drain 2ma, 6ma ? pci33 n/a 3.3 hstl18 class i, ii, iii n/a 1.8 hstl15 class i, iii n/a 1.5 sstl3 class i, ii n/a 3.3 sstl2 class i, ii n/a 2.5 sstl18 class i n/a 1.8 differential interfaces differential sstl3, class i, ii n/a 3.3 differential sstl2, class i, ii n/a 2.5 differential sstl18, class i n/a 1.8 differential hstl18, class i, ii, iii n/a 1.8 differential hstl15, class i, iii n/a 1.5 l vds n/a 2.5 blvds 1 n/a 2.5 l vpecl 1 n/a 3.3 rsds 1 n/a 2.5 1. emulated with external resistors. 2-32 architecture lattice semiconductor latticeecp/ec family data sheet con guration and testing the following section describes the con guration and testing features of the latticeecp/ec family of devices. ieee 1149.1-compliant boundary scan testability all latticeecp/ec devices have boundary scan cells that are accessed through an ieee 1149.1 compliant test access port (tap). this allows functional testing of the circuit board, on which the device is mounted, through a serial scan path that can access all critical logic nodes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test data to be captured and shifted out for veri cation. the test access port consists of dedicated i/os: tdi, tdo, tck and tms. the test access port has its own supply voltage v ccj and can operate with lvcmos3.3, 2.5, 1.8, 1.5 and 1.2 standards. f or more details on boundary scan test, please see information regarding additional technical documentation at the end of this data sheet. device con guration all latticeecp/ec devices contain two possible ports that can be used for device con guration. the test access port (tap), which supports bit-wide con guration, and the sysconfig port that supports both byte-wide and serial con guration. the tap supports both the ieee std. 1149.1 boundary scan speci cation and the ieee std. 1532 in-system con- guration speci cation. the sysconfig port is a 20-pin interface with six of the i/os used as dedicated pins and the rest being dual-use pins. when sysconfig mode is not used, these dual-use pins are available for general purpose i/o. there are four con guration options for latticeecp/ec devices: 1. industry standard spi memories. 2. industry standard byte wide ash and ispmach 4000 for control/addressing. 3. con guration from system microprocessor via the con guration bus or tap. 4. industry standard fpga board memory. on power-up, the fpga sram is ready to be con gured with the sysconfig port active. the ieee 1149.1 serial mode can be activated any time after power-up by sending the appropriate command through the tap port. once a con guration port is selected, that port is locked and another con guration port cannot be activated until the next power-up sequence. f or more information on device con guration, please see details of additional technical documentation at the end of this data sheet. internal logic analyzer capability (isptracy) all latticeecp/ec devices support an internal logic analyzer diagnostic feature. the diagnostic features provide capabilities similar to an external logic analyzer, such as programmable event and trigger condition and deep trace memory. this feature is enabled by lattice?s isptracy. the isptracy utility is added into the user design at com- pile time. f or more information on isptracy, please see information regarding additional technical documentation at the end of this data sheet. external resistor latticeecp/ec devices require a single external, 10k ohm +/- 1% value between the xres pin and ground. device con guration will not be completed if this resistor is missing. there is no boundary scan register on the e xternal resistor pad. 2-33 architecture lattice semiconductor latticeecp/ec family data sheet oscillator every latticeecp/ec device has an internal cmos oscillator which is used to derive a master serial clock for con- t guration. the oscillator and the master serial clock run continuously. the default value of the master serial clock is 2.5mhz. table 2-15 lists all the available master serial clock frequencies. when a different master serial clock is selected during the design process, the following sequence takes place: 1. user selects a different master serial clock frequency. 2. during con t guration the device starts with the default (2.5mhz) master serial clock frequency. 3. the clock con t guration settings are contained in the early con t guration bit stream. 4. the master serial clock frequency changes to the selected frequency once the clock con t guration bits are received. f or further information on the use of this oscillator for con t guration, please see details of additional technical docu- mentation at the end of this data sheet. ta b le 2-15. selectable master serial clock (cclk) frequencies during contguration density shifting the latticeecp/ec family has been designed to ensure that different density devices in the same package have the same pin-out. furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. in many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a lower density device. however, the exact details of the t nal resource utiliza- tion will impact the likely success in each case. cclk (mhz) cclk (mhz) cclk (mhz) 2.5* 13 45 4.3 15 51 5.4 20 55 6.9 26 60 8.1 30 130 9.2 34 ? 10.0 41 ? www.latticesemi.com 3-1 dc and switching_01.2 november 2004 preliminary data sheet ? 2004 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci t cations and information herein are subject to change without notice. recommended operating conditions absolute maximum ratings 1, 2, 3 1. stress above those listed under the ?absolute maximum ratings? may cause permanent damage to the device. functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci t cation is not implied. 2. compliance with the lattice thermal management document is required. 3. all voltages referenced to gnd. supply voltage v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 1.32v supply voltage v ccaux . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75v supply voltage v ccj . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 3.75v output supply voltage v ccio . . . . . . . . . . . . . . . . -0.5 to 3.75v input voltage applied 4 . . . . . . . . . . . . . . . . . . . . . . -0.5 to 4.25v i/o tristate voltage applied 4 . . . . . . . . . . . . . . . . . -0.5 to 3.75v storage temperature (ambient) . . . . . . . . . . . . . . -65 to 150c j unction temp. (tj) +125c 4. overshoot and undershoot of -2v to (v ihmax + 2) volts is permitted for a duration of <20ns. symbol parameter min. max. units v cc core supply voltage 1.14 1.26 v v ccaux a uxiliary supply voltage 3.135 3.465 v v ccio 1, 2 i/o driver supply voltage 1.140 3.465 v v ccj 1 supply voltage for ieee 1149.1 test access port 1.140 3.465 v t jcom j unction commercial operation 0 +85 c t jind j unction industrial operation -40 100 c 1. if v ccio or v ccj is set to 1.2v, they must be connected to the same power supply as v cc. if v ccio or v ccj is set to 3.3v, they must be con- nected to the same power supply as v ccaux . 2. see recommended voltages by i/o standard in subsequent table. hot socketing speci t cations 1, 2, 3, 4 1. insensitive to sequence of v cc, v ccaux and v ccio . however, assumes monotonic rise/fall rates for v cc, v ccaux and v ccio. 2. 0 v cc v cc (max), 0 v ccio v ccio (max) or 0 v ccaux v ccaux (max). 3. i dk is additive to i pu, i pw or i bh . 4. lvcmos and lvttl only. symbol parameter condition min. typ. max units i dk input or i/o leakage current 0 v in v ih (max) ? ? +/-1000 a latticeecp/ec family data sheet dc and switching characteristics 3-2 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet dc electrical characteristics over recommended operating conditions symbol parameter condition min. typ. max. units i il, i ih 1 input or i/o low leakage 0 # v in # (v ccio - 0.2v) ? ? 10 a (v ccio - 0.2v) # v in # 3.6v ? ? 40 a i pu i/o active pull-up current 0 # v in # 0.7 v ccio 30 ? 150 a i pd i/o active pull-down current v il (max) # v in # v ih (max) -30 ? -150 a i bhls bus hold low sustaining current v in = v il (max) 30 ? ? a i bhhs bus hold high sustaining current v in = 0.7v ccio -30 ? ? a i bhlo bus hold low overdrive current 0 # v in # v ih (max) ? ? 150 a i bhlh bus hold high overdrive current 0 # v in # v ih (max) ? ? -150 a v bht bus hold trip points 0 # v in # v ih (max) v il (max) ? v ih (min) v c1 i/o capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?8?pf c2 dedicated input capacitance 2 v ccio = 3.3v, 2.5v, 1.8v, 1.5v, 1.2v, v cc = 1.2v, v io = 0 to v ih (max) ?6?pf 1. input or i/o leakage current is measured with the pin con gured as an input or as an i/o with the output driver tri-stated. it is not measured with the output driver active. bus maintenance circuits are disabled. 2. t a 25 o c, f = 1.0mhz 3-3 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet supply current (standby) 1, 2, 3, 4 over recommended operating conditions 1. for further information on supply current, please see details of additional technical documentation at the end of this data s heet. 2. assumes all outputs are tristated, all inputs are con gured as lvcmos and held at the v ccio or gnd. 3. frequency 0mhz. 4. pattern represents typical design with 65% logic, 55% ebr, 10% routing utilization. 5. t j =25 o c, power supplies at nominal voltage. 6. per bank. symbol parameter devices typ. 5 max. units i cc core power supply current lfec1 ma lfec3 ma lfecp6/lfec6 ma lfecp10/lfec10 ma lfecp15/lfec15 ma lfecp20/lfec20 100 ma lfecp33/lfec33 ma lfecp40/lfec40 ma i ccaux a uxiliary power supply current lfec1 ma lfec3 ma lfecp6/lfec6 ma lfecp10/lfec10 ma lfecp15/lfec15 ma lfecp20/lfec20 15 ma lfecp33/lfec33 ma lfecp40/lfec40 ma i ccpll pll power supply current (per pll) lfec1, lfec3, lfec6, lfecp6, lfecp10, lfecp15, lfecp20, lfecp33, lfecp40, lfec10, lfec15, lfec20, lfec33, lfec40, 8ma i ccio bank power supply current 6 2ma i ccj v ccj power supply current 5 ma 3-4 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet initialization supply current 1,2,3,4,5,6 over recommended operating conditions 1. until done signal is active. 2. for further information on supply current, please see details of additional technical documentation at the end of this data s heet. 3. assumes all outputs are tristated, all inputs are con gured as lvcmos and held at the v ccio or gnd. 4. frequency 0mhz. 5. pattern represents typical design with 65% logic, 55% ebr, 10% routing utilization. 6. t j =25 o c, power supplies at nominal voltage. 7. per bank. symbol parameter devices typ. 6 max. units i cc core power supply current lfec1 ma lfec3 ma lfecp6/lfec6 ma lfecp10/lfec10 ma lfecp15/lfec15 ma lfecp20/lfec20 150 ma lfecp33/lfec33 ma lfecp40/lfec40 ma i ccaux a uxiliary power supply current lfec1 ma lfec3 ma lfecp6/lfecp6 ma lfecp10/lfec10 ma lfecp15/lfec15 ma lfecp20/lfec20 25 ma lfecp33/lfec33 ma lfecp40/lfec40 ma i ccpll pll power supply current (per pll) lfec1, lfec3, lfec6, lfecp6, lfecp10, lfecp15, lfecp20, lfecp33, lfecp40, lfec10, lfec15, lfec20, lfec33, lfec40, 12 ma i ccio bank power supply current 7 5ma i ccj v ccj power supply current 10 ma 3-5 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet sysio recommended operating conditions v ccio v ref (v) standard min. typ. max. min. typ. max. l vcmos 3.3 3.135 3.3 3.465 ? ? ? l vcmos 2.5 2.375 2.5 2.625 ? ? ? l vcmos 1.8 1.71 1.8 1.89 ? ? ? l vcmos 1.5 1.425 1.5 1.575 ? ? ? l vcmos 1.2 1.14 1.2 1.26 ? ? ? l vttl 3.135 3.3 3.465 ? ? ? pci 3.135 3.3 3.465 ? ? ? sstl18 class i 1.71 2.5 1.89 1.15 1.25 1.35 sstl2 class i, ii 2.375 2.5 2.625 1.15 1.25 1.35 sstl3 class i, ii 3.135 3.3 3.465 1.3 1.5 1.7 hstl15 class i 1.425 1.5 1.575 0.68 0.75 0.9 hstl15 class iii 1.425 1.5 1.575 ? 0.9 ? hstl 18 class i, ii 1.71 1.8 1.89 ? 0.9 ? hstl 18 class iii 1.71 1.8 1.89 ? 1.08 ? l vds 2.375 2.5 2.625 ? ? ? l vpecl 1 3.135 3.3 3.465 ? ? ? blvds 1 2.375 2.5 2.625 ? ? ? rsds 1 2.375 2.5 2.625 ? ? ? 1. inputs on chip. outputs are implemented with the addition of external resistors. 3-6 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet sysio single-ended dc electrical characteristics input/output standard v il v ih v ol max. (v) v oh min. (v) i ol 1 (ma) i oh 1 (ma) min. (v) max. (v) min. (v) max. (v) l vcmos 3.3 -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 l vttl -0.3 0.8 2.0 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 l vcmos 2.5 -0.3 0.7 1.7 3.6 0.4 v ccio - 0.4 20, 16, 12, 8, 4 -20, -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 l vcmos 1.8 -0.3 0.35v ccio 0.65v ccio 3.6 0.4 v ccio - 0.4 16, 12, 8, 4 -16, -12, -8, -4 0.2 v ccio - 0.2 0.1 -0.1 l vcmos 1.5 -0.3 0.35v ccio 0.65v ccio 3.6 0.4 v ccio - 0.4 8, 4 -8, -4 0.2 v ccio - 0.2 0.1 -0.1 l vcmos 1.2 -0.3 0.35v cc 0.65v cc 3.6 0.4 v ccio - 0.4 6, 2 -6, -2 0.2 v ccio - 0.2 0.1 -0.1 pci -0.3 0.3v ccio 0.5v ccio 3.6 0.1v ccio 0.9v ccio 1.5 -0.5 sstl3 class i -0.3 v ref - 0.2 v ref + 0.2 3.6 0.7 v ccio - 1.1 8 -8 sstl3 class ii -0.3 v ref - 0.2 v ref + 0.2 3.6 0.5 v ccio - 0.9 16 -16 sstl2 class i -0.3 v ref - 0.18 v ref + 0.18 3.6 0.54 v ccio - 0.62 7.6 -7.6 sstl2 class ii -0.3 v ref - 0.18 v ref + 0.18 3.6 0.35 v ccio - 0.43 15.2 -15.2 sstl18 class i -0.3 v ref - 0.125 v ref + 0.125 3.6 0.4 v ccio - 0.4 6.7 -6.7 hstl15 class i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 8 -8 hstl15 class iii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 24 -8 hstl18 class i -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 9.6 -9.6 hstl18 class ii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 16 -16 hstl18 class iii -0.3 v ref - 0.1 v ref + 0.1 3.6 0.4 v ccio - 0.4 24 -8 1. the average dc current drawn by i/os between gnd connections, or between the last gnd in an i/o bank and the end of an i/o ba nk, as shown in the logic signal connections table shall not exceed n * 8ma. where n is the number of i/os between bank gnd connection s or between the last gnd in a bank and the end of a bank. rev f 0.17 3-7 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet sysio differential electrical characteristics l vds over recommended operating conditions p arameter symbol parameter description test conditions min. typ. max. units v inp, v inm input voltage 0 ? 2.4 v v thd differential input threshold +/-100 ? ? mv v cm input common mode voltage 100mv # v thd v thd /2 1.2 1.8 v 200mv # v thd v thd /2 1.2 1.9 v 350mv # v thd v thd /2 1.2 2.0 v i in input current power on or power off ? ? +/-10 a v oh output high voltage for v op or v om r t = 100 ohm ? 1.38 1.60 v v ol output low voltage for v op or v om r t = 100 ohm 0.9v 1.03 ? v v od output voltage differential (v op - v om ), r t = 100 ohm 250 350 450 mv $ v od change in v od between high and low ??50 mv v os output voltage offset (v op - v om )/2, r t = 100 ohm 1.125 1.25 1.375 v $ v os change in v os between h and l ? ? 50 mv i osd output short circuit current v od = 0v driver outputs shorted ?? 6ma 3-8 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet differential hstl and sstl differential hstl and sstl outputs are implemented as a pair of complementary single-ended outputs. all allow- able single-ended output classes (class i and class ii) are supported in this mode. blvds the latticeecp/ec devices support blvds standard. this standard is emulated using complementary lvcmos outputs in conjunction with a parallel external resistor across the driver outputs. blvds is intended for use when m ulti-drop and bi-directional multi-point differential signaling is required. the scheme shown in figure 3-1 is one possible solution for bi-directional multi-point differential signals. figure 3-1. blvds multi-point output example ta b le 3-1. blvds dc conditions 1 over recommended operating conditions t ypical p arameter description zo = 45 zo = 90 units z out output impedance 100 100 ohm r tleft left end termination 45 90 ohm r tright right end termination 45 90 ohm v oh output high voltage 1.375 1.48 v v ol output low voltage 1.125 1.02 v v od output differential voltage 0.25 0.46 v v cm output common mode voltage 1.25 1.25 v i dc dc output current 11.2 10.2 ma 1. for input buffer, see lvds table. heavily loaded backplane, effective zo ~ 45 to 90 ohms differential 2.5v 80 80 80 80 80 80 45-90 ohms 45-90 ohms 80 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v 2.5v + - . . . + - . . . + - + - 3-9 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet l vpecl the latticeecp/ec devices support differential lvpecl standard. this standard is emulated using complemen- tary lvcmos outputs in conjunction with a parallel resistor across the driver outputs. the scheme shown in figure 3-2 is one possible solution for point-to-point signals. figure 3-2. differential lvpecl ta b le 3-2. lvpecl dc conditions 1 over recommended operating conditions f or further information on lvpecl, blvds and other differential interfaces please see details of additional techni- cal information at the end of this data sheet. p arameter description typical units z out output impedance 100 ohm r p driver parallel resistor 150 ohm r t receiver termination 100 ohm v oh output high voltage 2.03 v v ol output low voltage 1.27 v v od output differential voltage 0.76 v v cm output common mode voltage 1.65 v z back back impedance 85.7 ohm i dc dc output current 12.7 ma 1. for input buffer, see lvds table. transmission line, zo = 100 ohm differential 100 ohms 100 ohms 100 ohms off-chip 3.3v 3.3v + - ~150 ohms 3-10 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet rsds the latticeecp/ec devices support differential rsds standard. this standard is emulated using complementary l vcmos outputs in conjunction with a parallel resistor across the driver outputs. the scheme shown in figure 3-3 is one possible solution for rsds standard implementation. use lvds25e mode with suggested resistors for rsds operation. resistor values in figure 3-3 are industry standard values for 1% resistors. figure 3-3. rsds (reduced swing differential standard) ta b le 3-3. rsds dc conditions 5v tolerant input buffer the input buffers of the latticeecp/ec family of devices can support 5v signals by using a pci clamp and an e xternal series resistor as shown in figure 3-4. figure 3-4. 5 v tolerant input buffer p arameter description typical units z out output impedance 20 ohm r s driver series resistor 294 ohm r p driver parallel resistor 121 ohm r t receiver termination 100 ohm v oh output high voltage 1.35 v v ol output low voltage 1.15 v v od output differential voltage 0.20 v v cm output common mode voltage 1.25 v z back back impedance 101.5 ohm i dc dc output current 3.66 ma 100 294 294 on-chip emulated rsds buffer vccio = 2.5v vccio = 2.5v zo = 100 + - 121 off-chip external resistor 5v signals from legacy systems v ccio 3-11 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet figure 3-5. typical pci clamp current voltage (v) 100 200 300 400 50 0 1 0 2345678 150 250 350 current (ma) 3-12 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet t ypical building block function performance pin-to-pin performance (lvcmos25 12ma drive) function -5 timing units basic functions 16 bit decoder 6.2 ns 32 bit decoder 7.2 ns 64 bit decoder 7.7 ns 4:1 mux 4.8 ns 8:1 mux 5.1 ns 16:1 mux 6.1 ns 32:1 mux 6.5 ns combinatorial (pin to lut to pin) 5.3 ns register-to-register performance function -5 timing units basic functions 16 bit decoder 331 mhz 32 bit decoder 277 mhz 64 bit decoder 240 mhz 4:1 mux 727 mhz 8:1 mux 482 mhz 16:1 mux 439 mhz 32:1 mux 382 mhz 8-bit adder 391 mhz 16-bit adder 337 mhz 64-bit adder 190 mhz 16-bit counter 410 mhz 32-bit counter 315 mhz 64-bit counter 215 mhz 64-bit accumulator 155 mhz embedded memory functions 256x36 single port ram 280 mhz 512x18 true-dual port ram 280 mhz distributed memory functions 16x2 single port ram 549 mhz 64x2 single port ram 259 mhz 128x4 single port ram 205 mhz 32x2 pseudo-dual port ram 360 mhz 64x4 pseudo-dual port ram 301 mhz dsp function 1 9x9 pipelined multiply/accumulate 250 mhz 18x18 pipelined mutiply/accumulate 230 mhz 36x36 pipelined mutiply 210 mhz 1. applies to latticeecp devices only. 2. the above timing numbers were generated using isplever tool, exact performance may vary with design and tool version. the too l uses internal parameters that have been characterized but are not tested on every device. 3-13 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet derating timing tables logic timing provided in the following sections of the data sheet and the isplever design tools are worst-case n umbers in the operating range. actual delays at nominal temperature and voltage for best-case process, can be m uch better than the values given in the tables. to calculate logic timing numbers at a particular temperature and v oltage multiply the noted numbers with the derating factors provided below. the junction temperature for the fpga depends on the power dissipation by the device, the package thermal char- acteristics ( % ja ), and the ambient temperature, as calculated with the following equation: t jmax = t amax + (power * % ja ) the user must determine this temperature and then use it to determine the derating factor based on the following derating tables: t j c. ta b le 3-4. delay derating table for internal blocks t j c commercial t j c industrial po wer supply voltage 1.14v 1.2v 1.26v ? -40 0.82 0.77 0.71 ? -25 0.82 0.76 0.71 02 0 0.89 0.83 0.78 25 45 0.93 0.87 0.81 85 105 1.00 0.94 0.89 100 115 1.00 0.95 0.90 110 ? 1.00 0.95 0.90 125 ? 1.02 0.96 0.91 3-14 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet latticeecp/ec external switching characteristics over recommended operating conditions figure 3-6. ddr timings p arameter description device -5 -4 -3 units min. max. min. max. min. max. general i/o pin parameters (using primary clock without pll) 1 t co clock to output - pio output register lfec20 ? 5.71 ? 6.85 ? 7.99 ns t su clock to data setup - pio input register lfec20 0.00 ? 0.00 ? 0.00 ? ns t h clock to data hold - pio input register lfec20 3.41 ? 4.09 ? 4.77 ? ns t su_del clock to data setup - pio input register with data input delay lfec20 3.84 ? 4.62 ? 5.38 ? ns t h_del clock to data hold - pio input register with input data delay lfec20 -0.44 ? -0.54 ? -0.61 ? ns f max_io l vds i/o buffer frequency lfec20 ? 420 ? 378 ? 340 mhz ddr i/o pin parameters 2, 3 t dv adq 4 data valid after dqs (ddr read) lfec20 ? 0.192 ? 0.192 ? 0.192 ui t d vedq 4 data hold after dqs (ddr read) lfec20 0.668 ? 0.668 ? 0.668 ? ui t dqvbs data valid before dqs lfec20 0.2 ? 0.2 ? 0.2 ? ui t dqvas data valid after dqs lfec20 0.2 ? 0.2 ? 0.2 ? ui f max_ddr ddr clock frequency lfec20 95 200 95 166 95 133 mhz primary and secondary clock f max_pri f requency for primary clock tree lfec20 ? 420 ? 378 ? 340 mhz t w_pri clock pulse width for primary clock lfec20 1.19 ? 1.19 ? 1.19 ? ns t skew_pri primary clock skew within an i/o bank lfec20 ? 250 ? 300 ? 350 ps 1. general timing numbers based on lvcmos2.5v, 12 ma. 2. ddr timing numbers based on sstl i/o. 3. ddr speci cations are characterized but not tested. 4. ui is average bit period. rev f 0.17 t dqvas t dqvbs dq and dqs write timings t dqs dq dqs dq dved q t dvadq dq and dqs read timings 3-15 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet latticeecp/ec internal timing parameters 1 over recommended operating conditions p arameter description -5 -4 -3 units min. max. min. max. min. max. pfu/pff logic mode timing t lut4_pfu lut4 delay (a to d inputs to f output) - 0.25 - 0.31 - 0.36 ns t lut6_pfu lut6 delay (a to d inputs to ofx output) - 0.55 - 0.66 - 0.77 ns t lsr_pfu set/reset to output of pfu - 0.81 - 0.98 - 1.14 ns t sum_pfu clock to mux (m0,m1) input setup time 0.08 - 0.10 - 0.11 - ns t hm_pfu clock to mux (m0,m1) input hold time -0.06 - -0.07 - -0.08 - ns t sud_pfu clock to d input setup time 0.11 - 0.14 - 0.16 - ns t hd_pfu clock to d input hold time -0.04 - -0.04 - -0.05 - ns t ck2q_pfu clock to q delay, d-type register con gura- tion - 0.43 - 0.51 - 0.60 ns t le2q_pfu clock to q delay latch con guration - 0.54 - 0.65 - 0.76 ns t ld2q_pfu d to q throughput delay when latch is enabled - 0.50 - 0.60 - 0.69 ns pfu memory mode timing t coram_pfu clock to output - 0.43 - 0.51 - 0.60 ns t sudata_pfu data setup time -0.25 - -0.30 - -0.34 - ns t hdata_pfu data hold time -0.06 - -0.07 - -0.08 - ns t suaddr_pfu address setup time -0.66 - -0.79 - -0.92 - ns t haddr_pfu address hold time -0.27 - -0.33 - -0.38 - ns t suwren_pfu write/read enable setup time -0.30 - -0.36 - -0.42 - ns t hwren_pfu write/read enable hold time -0.21 - -0.25 - -0.29 - ns pic timing pio input/output buffer timing t in_pio input buffer delay - 0.56 - 0.67 - 0.78 ns t out_pio output buffer delay - 2.07 - 2.49 - 2.90 ns iologic input/output timing t sui_pio input register setup time (data before clock) - 0.12 - 0.14 - 0.17 ns t hi_pio input register hold time (data after clock) - -0.09 - -0.11 - -0.13 ns t coo_pio output register clock to output delay - 0.82 - 0.98 - 1.15 ns t suce_pio input register clock enable setup time - -0.02 - -0.02 - -0.03 ns t hce_pio input register clock enable hold time - 0.12 - 0.14 - 0.17 ns t sulsr_pio set/reset setup time 0.10 - 0.12 - 0.14 - ns t hlsr_pio set/reset hold time -0.24 - -0.29 - -0.34 - ns ebr timing t co_ebr clock to output from address or data - 3.82 - 4.58 - 5.34 ns t coo_ebr clock to output from ebr output register - 0.74 - 0.88 - 1.03 ns t sudata_ebr setup data to ebr memory -0.34 - -0.41 - -0.48 - ns t hdata_ebr hold data to ebr memory 0.37 - 0.44 - 0.52 - ns t suaddr_ebr setup address to ebr memory -0.34 - -0.41 - -0.48 - ns t haddr_ebr hold address to ebr memory 0.37 - 0.45 - 0.52 - ns t suwren_ebr setup write/read enable to pfu memory -0.22 - -0.26 - -0.30 - ns 3-16 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet t hwren_ebr hold write/read enable to pfu memory 0.23 - 0.28 - 0.33 - ns t suce_ebr clock enable setup time to ebr output register 0.28 - 0.34 - 0.40 - ns t hce_ebr clock enable hold time to ebr output register -0.24 - -0.29 - -0.34 - ns t rsto_ebr reset to output delay time from ebr out- put register - 1.00 - 1.20 - 1.40 ns pll parameters t rstrec reset recovery to rising clock - - - ns t rstsu reset signal setup time - - - ns t rstw reset signal pulse width 10.0 - 10.0 - 10.0 - ns dsp block timing 2 t sui_dsp input register setup time - -0.44 - -0.35 - -0.27 ns t hi_dsp input register hold time - 0.80 - 0.96 - 1.12 ns t sup_dsp pipeline register setup time - 3.31 - 3.98 - 4.64 ns t hp_dsp pipeline register hold time - 0.80 - 0.96 - 1.12 ns t suo_dsp output register setup time - 6.72 - 8.07 - 9.41 ns t ho_dsp output register hold time - 0.80 - 0.96 - 1.12 ns t coi_dsp input register clock to output time - 8.33 - 10.35 - 12.07 ns t cop_dsp pipeline register clock to output time - 4.80 - 5.89 - 6.87 ns t coo_dsp output register clock to output time - 1.47 - 1.77 - 2.06 ns t coovrfl_dsp over ow register clock to output time - 1.47 - 1.77 - 2.06 ns t suadsub adsub setup time - 3.31 - 3.98 - 4.64 ns t hadsub adsub hold time - 0.71 - 0.86 - 1.00 ns t susign sign setup time - 3.31 - 3.98 - 4.64 ns t hsign sign hold time - 0.80 - 0.96 - 1.12 ns t suaccsload accumulator load setup time - 3.31 - 3.98 - 4.64 ns t haccsload accumulator load hold time - 0.80 - 0.96 - 1.12 ns 1. internal parameters are characterized but not tested on every device. 2. these parameters apply to latticeecp devices only. rev f 0.17 latticeecp/ec internal timing parameters 1 (continued) over recommended operating conditions p arameter description -5 -4 -3 units min. max. min. max. min. max. 3-17 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet timing diagrams pfu timing diagrams figure 3-7. slice single/dual port write cycle timing figure 3-8. slice single /dual port read cycle timing ck d wre d di[1:0] do[1:0] ad ad[3:0] old data wre d do[1:0] ad ad[3:0] old data 3-18 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet ebr memory timing diagrams figure 3-9. read/write mode (normal) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. figure 3-10. read/write mode with input and output registers a0 a1 a0 a1 d0 d1 doa a0 t access t access t su t h d0 d1 d0 dia ada wea csa clka a0 a1 a0 a0 d0 d1 d0 d0 doa output is only updated during a read cycle a1 d1 d0 d1 mem(n) data from previous read mem(n) data from previous read dia ada wea csa clka doa doa (regs) t su t h t access t access 3-19 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet figure 3-11. read before write (sp read/write on port a, input registers only) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. figure 3-12. write through (sp read/write on port a, input registers only) note: input data and address are registered at the positive edge of the clock and output data appears after the positive edge o f the clock. a0 a1 a0 a1 d0 d1 d2 doa a0 d2 d3 d1 old a0 data old a1 data d0 d1 dia ada wea csa clka t su t h t access t access t access t access t access a0 a1 a0 d0 d1 d4 t su t access t access t access t h d2 d3 d4 d0 d1 d2 data from prev read or write three consecutive writes to a0 d3 doa dia ada wea csa clka t access 3-20 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet latticeecp/ec family timing adders 1, 2, 3 over recommended operating conditions buffer type description -5 -4 -3 units input adjusters l vds25 lvds 0.41 0.50 0.58 ns blvds25 blvds 0.41 0.50 0.58 ns l vpecl33 lvpecl 0.50 0.60 0.70 ns hstl18_i hstl_18 class i 0.41 0.49 0.57 ns hstl18_ii hstl_18 class ii 0.41 0.49 0.57 ns hstl18_iii hstl_18 class iii 0.41 0.49 0.57 ns hstl18d_i differential hstl 18 class i 0.37 0.44 0.52 ns hstl18d_ii differential hstl 18 class ii 0.37 0.44 0.52 ns hstl18d_iii differential hstl 18 class iii 0.37 0.44 0.52 ns hstl15_i hstl_15 class i 0.40 0.48 0.56 ns hstl15_iii hstl_15 class iii 0.40 0.48 0.56 ns hstl15d_i differential hstl 15 class i 0.37 0.44 0.51 ns hstl15d_iii differential hstl 15 class iii 0.37 0.44 0.51 ns sstl33_i sstl_3 class i 0.46 0.55 0.64 ns sstl33_ii sstl_3 class ii 0.46 0.55 0.64 ns sstl33d_i differential sstl_3 class i 0.39 0.47 0.55 ns sstl33d_ii differential sstl_3 class ii 0.39 0.47 0.55 ns sstl25_i sstl_2 class i 0.43 0.51 0.60 ns sstl25_ii sstl_2 class ii 0.43 0.51 0.60 ns sstl25d_i differential sstl_2 class i 0.38 0.45 0.53 ns sstl25d_ii differential sstl_2 class ii 0.38 0.45 0.53 ns sstl18_i sstl_18 class i 0.40 0.48 0.56 ns sstl18d_i differential sstl_18 class i 0.37 0.44 0.51 ns l vttl33 lvttl 0.07 0.09 0.10 ns l vcmos33 lvcmos 3.3 0.07 0.09 0.10 ns l vcmos25 lvcmos 2.5 0.00 0.00 0.00 ns l vcmos18 lvcmos 1.8 0.07 0.09 0.10 ns l vcmos15 lvcmos 1.5 0.24 0.29 0.33 ns l vcmos12 lvcmos 1.2 1.27 1.52 1.77 ns pci33 pci 0.07 0.09 0.10 ns output adjusters l vds25e lvds 2.5 e -0.03 -0.04 -0.04 ns l vds25 lvds 2.5 -0.59 -0.71 -0.83 ns blvds25 blvds 2.5 0.18 0.22 0.26 ns l vpecl33 lvpecl 3.3 0.05 0.06 0.07 ns hstl18_i hstl_18 class i -0.25 -0.30 -0.35 ns hstl18_ii hstl_18 class ii -0.09 -0.11 -0.13 ns hstl18_iii hstl_18 class iii 0.00 0.01 0.01 ns hstl18d_i differential hstl 18 class i -0.25 -0.30 -0.35 ns hstl18d_ii differential hstl 18 class ii -0.09 -0.11 -0.13 ns hstl18d_iii differential hstl 18 class iii 0.00 0.01 0.01 ns 3-21 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet hstl15_i hstl_15 class i -0.07 -0.08 -0.09 ns hstl15_ii hstl_15 class ii 0.00 0.00 0.00 ns hstl15_iii hstl_15 class iii -0.05 -0.06 -0.07 ns hstl15d_i differential hstl 15 class i -0.07 -0.08 -0.09 ns hstl15d_iii differential hstl 15 class iii -0.05 -0.06 -0.07 ns sstl33_i sstl_3 class i -0.20 -0.24 -0.28 ns sstl33_ii sstl_3 class ii 0.25 0.30 0.35 ns sstl33d_i differential sstl_3 class i -0.20 -0.24 -0.28 ns sstl33d_ii differential sstl_3 class ii 0.25 0.30 0.35 ns sstl25_i sstl_2 class i -0.10 -0.11 -0.13 ns sstl25_ii sstl_2 class ii 0.10 0.12 0.14 ns sstl25d_i differential sstl_2 class i -0.10 -0.11 -0.13 ns sstl25d_ii differential sstl_2 class ii 0.10 0.12 0.14 ns sstl18_i sstl_1.8 class i -0.14 -0.17 -0.20 ns sstl18d_i differential sstl_1.8 class i -0.14 -0.17 -0.20 ns l vttl33_4ma lvttl 4ma drive -0.06 -0.07 -0.09 ns l vttl33_8ma lvttl 8ma drive -0.05 -0.07 -0.08 ns l vttl33_12ma lvttl 12ma drive -0.06 -0.07 -0.08 ns l vttl33_16ma lvttl 16ma drive -0.05 -0.07 -0.08 ns l vttl33_20ma lvttl 20ma drive -0.07 -0.09 -0.10 ns l vcmos33_4ma lvcmos 3.3 4ma drive -0.06 -0.07 -0.09 ns l vcmos33_8ma lvcmos 3.3 8ma drive -0.05 -0.07 -0.08 ns l vcmos33_12ma lvcmos 3.3 12ma drive -0.06 -0.07 -0.08 ns l vcmos33_16ma lvcmos 3.3 16ma drive -0.05 -0.07 -0.08 ns l vcmos33_20ma lvcmos 3.3 20ma drive -0.07 -0.09 -0.10 ns l vcmos25_4ma lvcmos 2.5 4ma drive 0.04 0.05 0.05 ns l vcmos25_8ma lvcmos 2.5 8ma drive 0.03 0.03 0.04 ns l vcmos25_12ma lvcmos 2.5 12ma drive 0.00 0.00 0.00 ns l vcmos25_16ma lvcmos 2.5 16ma drive 0.03 0.03 0.04 ns l vcmos25_20ma lvcmos 2.5 20ma drive -0.05 -0.06 -0.07 ns l vcmos18_4ma lvcmos 1.8 4ma drive 0.07 0.08 0.10 ns l vcmos18_8ma lvcmos 1.8 8ma drive 0.07 0.08 0.09 ns l vcmos18_12ma lvcmos 1.8 12ma drive 0.06 0.07 0.09 ns l vcmos18_16ma lvcmos 1.8 16ma drive 0.07 0.08 0.09 ns l vcmos15_4ma lvcmos 1.5 4ma drive 0.12 0.14 0.16 ns l vcmos15_8ma lvcmos 1.5 8ma drive 0.11 0.13 0.15 ns l vcmos12_2ma lvcmos 1.2 2ma drive 0.22 0.26 0.31 ns l vcmos12_6ma lvcmos 1.2 6ma drive 0.21 0.25 0.29 ns l vcmos12_4ma lvcmos 1.2 4ma drive 0.22 0.26 0.31 ns pci33 pci33 2.00 2.40 2.80 ns 1. timing adders are characterized but not tested on every device. 2. lvcmos timing measured with the load speci ed in switching test conditions table. 3. all other standards according to the appropriate speci cation. rev f 0.17 latticeecp/ec family timing adders 1, 2, 3 (continued) over recommended operating conditions buffer type description -5 -4 -3 units 3-22 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet sysclock pll timing over recommended operating conditions p arameter descriptions conditions min. typ. max. units f in input clock frequency (clki, clkfb) 25 ? 420 mhz f out output clock frequency (clkop, clkos) 25 ? 420 mhz f out2 k-divider output frequency (clkok) 0.195 ? 210 mhz f vco pll vco frequency 420 ? 840 mhz f pfd phase detector input frequency 25 ? ? mhz ac characteristics t dt output clock duty cycle default duty cycle elected 3 45 50 55 % t ph 4 output phase accuracy ? ? tbd ui t opjit 1 output clock period jitter f out >= 100mhz ? ? +/- 125 ps f out < 100mhz ? ? 0.02 uipp t sk input clock to output clock skew divider ratio = integer ? ? +/- 200 ps t w output clock pulse width at 90% or 10% 3 1??ns t lock 2 pll lock-in time ? ? 150 us t pa programmable delay unit 100 250 400 ps t ipjit input clock period jitter ? ? +/- 200 ps t fbkdly external feedback delay ? ? 10 ns t hi input clock high time 90% to 90% 0.5 ? ? ns t lo input clock low time 10% to 10% 0.5 ? ? ns t rst rst pulse width 10 ? ? ns 1. jitter sample is taken over 10,000 samples of the primary pll output with clean reference clock. 2. output clock is valid after tlock for pll reset and dynamic delay adjustment. 3. using lvds output buffers. 4. relative to clkop. rev f 0.17 3-23 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet latticeecp/ec sysconfig port timing speci cations over recommended operating conditions p arameter description min max units sysconfig byte data flow t sucbdi byte d[0:7] setup time to cclk 7 ? ns t hcbdi byte d[0:7] hold time to cclk 1 ? ns t codo clock to dout in flowthrough mode ? tbd ns t sucs cs[0:1] setup time to cclk 7 ? ns t hcs cs[0:1] hold time to cclk 1 ? ns t suwd write signal setup time to cclk 7 ? ns t hwd write signal hold time to cclk 1 ? ns t dcb cclk to busy delay time ? 12 ns t cord clock to out for read data ? 12 ns sysconfig byte slave clocking t bsch byte slave clock minimum high pulse 6 ? ns t bscl byte slave clock minimum low pulse 6 ? ns t bscyc byte slave clock cycle time 15 ? ns sysconfig serial (bit) data flow t suscdi din setup time to cclk slave mode 7 ? ns t hscdi din hold time to cclk slave mode 1 ? ns t codo clock to dout in flowthrough mode ? 12 ns t sumcdi din setup time to cclk master mode 7 ? ns t hmcdi din hold time to cclk master mode 1 ? ns sysconfig serial slave clocking t ssch serial slave clock minimum high pulse 6 ? ns t sscl serial slave clock minimum low pulse 6 ? ns sysconfig por, initialization and wake up t icfg minimum vcc to init high ? 50 ms t vmc time from t icfg to valid master clock ? 2 us t prgmrj programb pin pulse rejection ? 10 ns t prgm programb low time to start con guration 25 ? ns t dinit programb high to init high delay ? 1 ms t dppinit delay time from programb low to init low ? 37 ns t dppdone delay time from programb low to done low ? 37 ns t iodiss user i/o disable from programb low ? 25 ns t ioenss user i/o enabled time from cclk edge during wake-up sequence ? 25 ns t mwc additional wake master clock signals after done pin high 120 ? cycles sysconfig spi port t cfgx init high to cclk low ? 1 s t csspi init high to csspin low ? 2 us t cscclk cclk low before csspin low 0 - ns t socdo cclk low to output valid ? 15 ns t soe csspin active setup time 300 ? ns t cspid csspin low to first clock edge setup time 300+3cyc 600+6cyc ns f maxspi max frequency for spi ? 20 mhz 3-24 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet rev f 0.18 figure 3-13. sysconfig spi port sequence t suspi sospi data setup time before cclk 7 ? ns t hspi sospi data hold time after cclk 2 ? ns master clock frequency selected v alue -30% selected v alue +30% mhz duty cycle 40 60 % latticeecp/ec sysconfig port timing speci cations (continued) over recommended operating conditions p arameter description min max units vcc t icfg t cscclk t soe t socdo t cspid t csspi t cfgx t dint t dppint programn done initn csspin cclk sispi/busy d7/spid0 d7 d5 d4 d3 d2 d1 d0 d6 xxx valid bitstream clock 127 clock 128 0 1 2 3 4 5 6 7 0 t prgm capture cfgx capture opcode t dppdone 3-25 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet jtag port timing speci cations over recommended operating conditions rev f 0.17 symbol parameter min. max. units f max tck clock frequency - 25 mhz t btcp tck [bscan] clock pulse width 40 - ns t btcph tck [bscan] clock pulse width high 20 - ns t btcpl tck [bscan] clock pulse width low 20 - ns t bts tck [bscan] setup time 8 - ns t bth tck [bscan] hold time 10 - ns t btrf tck [bscan] rise/fall time 50 - mv/ns t btco t ap controller falling edge of clock to valid output - 10 ns t btcodis t ap controller falling edge of clock to valid disable - 10 ns t btcoen t ap controller falling edge of clock to valid enable - 10 ns t btcrs bscan test capture register setup time 8 - ns t btcrh bscan test capture register hold time 25 - ns t b utco bscan test update register, falling edge of clock to valid output - 25 ns t btuodis bscan test update register, falling edge of clock to valid disable - 25 ns t btupoen bscan test update register, falling edge of clock to valid enable - 25 ns 3-26 dc and switching characteristics lattice semiconductor latticeecp/ec family data sheet switching test conditions figure 3-14 shows the output test load that is used for ac testing. the speci c values for resistance, capacitance, v oltage, and other test conditions are shown in table 3-5. figure 3-14. output test load, lvttl and lvcmos standards ta b le 3-5. test fixture required components, non-terminated interfaces t est condition r 1 c l timing ref. v t l vttl and other lvcmos settings (l -> h, h -> l) & 0pf l vcmos 3.3 = 1.5v ? l vcmos 2.5 = v ccio /2 ? l vcmos 1.8 = v ccio /2 ? l vcmos 1.5 = v ccio /2 ? l vcmos 1.2 = v ccio /2 ? l vcmos 2.5 i/o (z -> h) 188 ' 0pf v ccio /2 v ol l vcmos 2.5 i/o (z -> l) v ccio /2 v oh l vcmos 2.5 i/o (h -> z) v oh - 0.15 v ol l vcmos 2.5 i/o (l -> z) v ol + 0.15 v oh note: output test conditions for all other interfaces are determined by the respective standards. dut v t r1 cl* test point *cl includes test fixture and probe capacitance www.latticesemi.com 4-1 pinout information_01.2 november 2004 preliminary data sheet ? 2004 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci t cations and information herein are subject to change without notice. signal descriptions signal name i/o descriptions general purpose p[edge] [row/column number*]_[a/b] i/o [edge] indicates the edge of the device on which the pad is located. valid edge designations are l (left), b (bottom), r (right), t (top). [row/column number] indicates the pfu row or the column of the device on which the pic exists. when edge is t (top) or (bottom), only need to specify row number. when edge is l (left) or r (right), only need to specify col- umn number. [a/b] indicates the pio within the pic to which the pad is connected. some of these user-programmable pins are shared with special function pins. these pin when not used as special purpose pins can be programmed as i/os for user logic. during con t guration the user-programmable i/os are tri-stated with an inter- nal pull-up resistor enabled. if any pin is not used (or not bonded to a pack- age pin), it is also tri-stated with an internal pull-up resistor enabled after con t guration. gsrn i global reset signal (active low). any i/o pin can be gsrn. nc ? no connect. gnd ? ground. dedicated pins. v cc ?p ow er supply pins for core logic. dedicated pins. v ccaux ? a uxiliary power supply pin. it powers all the differential and referenced input b uffers. dedicated pins. v cciox ?p ow er supply pins for i/o bank x. dedicated pins. v ref1_x, v ref2_x ? reference supply pins for i/o bank x. pre-determined pins in each bank are as assigned v ref inputs. when not used, they may be used as i/o pins. xres ? 10k ohm +/-1% resistor must be connected between this pad and ground. pll and clock functions (used as user programmable i/o pins when not in use for pll or clock pins) [loc][num]_pll[t, c]_in_a i reference clock (pll) input pads: ulm, llm, urm, lrm, num = row from center, t = true and c = complement, index a,b,c...at each side. [loc][num]_pll[t, c]_fb_a i optional feedback (pll) input pads: ulm, llm, urm, lrm, num = row from center, t = true and c = complement, index a,b,c...at each side. pclk[t, c]_[n:0]_[3:0] i primary clock pads, t = true and c = complement, n per side, indexed by bank and 0,1,2,3 within bank. [loc]dqs[num] i dqs input pads: t (top), r (right), b (bottom), l (left), dqs, num = ball function number. any pad can be con t gured to be output. t est and programming (dedicated pins) tms i t est mode select input, used to control the 1149.1 state machine. pull-up is enabled during con t guration. tck i t est clock input pin, used to clock the 1149.1 state machine. no pull-up enabled. latticeecp/ec family data sheet pinout information 4-2 pinout information lattice semiconductor latticeecp/ec family data sheet tdi i t est data in pin. used to load data into device using 1149.1 state machine. after power-up, this tap port can be activated for con guration by sending appropriate command. (note: once a con guration port is selected it is locked. another con guration port cannot be selected until the power-up sequence). pull-up is enabled during con guration. tdo o output pin. test data out pin used to shift data out of device using 1149.1. v ccj ?v ccj - the power supply pin for jtag test access port. con guration pads (used during sysconfig) cfg[2:0] i mode pins used to specify con guration modes values latched on rising edge of initn. during con guration, a pull-up is enabled. these are dedicated pins. initn i/o open drain pin. indicates the fpga is ready to be con gured. during con g- uration, a pull-up is enabled. it is a dedicated pin. programn i initiates con guration sequence when asserted low. this pin always has an active pull-up. this is a dedicated pin. done i/o open drain pin. indicates that the con guration sequence is complete, and the startup sequence is in progress. this is a dedicated pin. cclk i/o con guration clock for con guring an fpga in sysconfig mode. b usy/sispi i/o read control command in spi3 or spix mode. csn i sysconfig chip select (active low). during con guration, a pull-up is enabled. cs1n i sysconfig chip select (active low). during con guration, a pull-up is enabled. writen i write data on parallel port (active low). d[7:0]/spid[0:7] i/o sysconfig port data i/o. dout/cson o output for serial con guration data (rising edge of cclk) when using sysconfig port. di/csspin i input for serial con guration data (clocked with cclk) when using syscon- fig port. during con guration, a pull-up is enabled. signal descriptions (cont.) signal name i/o descriptions 4-3 pinout information lattice semiconductor latticeecp/ec family data sheet pics and ddr data (dq) pins associated with the ddr strobe (dqs) pin pics associated with dqs strobe pio within pic ddr strobe (dqs) and data (dq) pins p[edge] [n-4] adq bdq p[edge] [n-3] adq bdq p[edge] [n-2] adq bdq p[edge] [n-1] adq bdq p[edge] [n] a [edge]dqsn bdq p[edge] [n+1] adq bdq p[edge] [n+2] adq bdq p[edge] [n+3] adq bdq notes: 1. ?n? is a row/column pic number 2. the ddr interface is designed for memories that support one dqs strobe per eight bits of data. in some packages, all the potential ddr data (dq) pins may not be available. 3. pic numbering de nitions are provided in the ?signal names? column of the signal descrip- tions table. 4-4 pinout information lattice semiconductor latticeecp/ec family data sheet pin information summary lfecp6/ec6 lfecp20/ec20 pin type 144-tqfp 208-pqfp 256-fpbga 484-fpbga 484-fpbga 672-fpbga single ended user i/o 97 147 195 224 360 400 differential pair user i/o 72 97 97 112 180 200 con guration dedicated 13 13 13 13 13 13 muxed 48 48 48 48 56 56 ta p 555555 dedicated (total without supplies) 110 160 208 373 373 509 v cc 4410 20 20 32 v ccaux 24212 12 20 v ccio bank0 232446 bank1 222446 bank2 122446 bank3 222446 bank4 222446 bank5 232446 bank6 222446 bank7 122446 gnd, gnd0-gnd7 14 18 20 44 44 63 nc 0 4 0 139 3 96 single ended/ differential i/o per bank bank0 14 26 32 32 48 64 bank1 13 17 18 32 48 48 bank2 8 14 16 16 40 40 bank3 13 16 32 32 44 48 bank4 14 17 17 32 48 48 bank5 13 26 32 32 48 64 bank6 14 16 32 32 44 48 bank7 8 15 16 16 40 40 v ccj 111111 note: during con guration the user-programmable i/os are tri-stated with an internal pull-up resistor enabled. if any pin is not used (or not bonded to a package pin), it is also tri-stated with an internal pull-up resistor enabled after con guration. 4-5 pinout information lattice semiconductor latticeecp/ec family data sheet po wer supply and nc connections signals 144 tqfp 208 pqfp 256 fpbga vcc 11, 13, 92, 99 24, 26, 128, 135 e12, e5, e8, m12, m5, m9, f6, f11, l11, l6 vccio0 136, 143 187, 197, 208 f7, f8 vccio1 110, 125 157, 176 f9, f10 vccio2 108 145, 155 g11, h11 vccio3 73, 84 106, 120 j11, k11 vccio4 55, 71 85, 104 l9, l10 vccio5 38, 44 53, 64, 74 l7, l8 vccio6 24, 36 37, 51 j6, k6 vccio7 1 2, 13 g6, h6 vccj 19 32 l4 vccaux 54, 126 22, 84, 136, 177 b15, r2 gnd, gnd0-gnd7 12, 15, 28, 37, 52, 63, 72, 80, 96, 98, 109, 117, 128, 144 1, 18, 25, 28, 41, 52, 72, 82, 93, 105, 116, 132, 134, 138, 156, 168, 179, 189 a1, a16, g10, g7, g8, g9, h10, h7, h8, h9, j10, j7, j8, j9, k10, k7, k8, k9, t1, t16 nc --- 4-6 pinout information lattice semiconductor latticeecp/ec family data sheet po wer supply and nc connections signals 484 fpbga 672 fpbga vcc j6, j7, j16, j17, k6, k7, k16, k17, l6, l17, m6, m17, n6, n7, n16, n17, p6, p7, p16, p17 h8, h9, h10, h11, h16, h17, h18, h19, j9, j18, k8, k19, l8, l19, m19, n7, r7, r20, t19, u8, u19, v8, v18, v9, w8, w9, w10, w11, w16, w17, w18, w19 vccio0 g11, h9, h10, h11 h12, h13, j10, j11, j12, j13 vccio1 g12, h12, h13, h14 h14, h15, j14, j15, j16, j17 vccio2 j15, k15, l15, l16 k17, k18, l18, m18, n18, n19 vccio3 m15, m16, n15, p15 p18, p19, r18, r19, t8, u18 vccio4 r12, r13, r14, t12 v14, v15, v16, v17, w14, w15 vccio5 r9, r10, r11, t11 v10, v11, v12, v13, w12, w13 vccio6 m7, m8, n8, p8 p8, p9, r8, r9, t9, u9 vccio7 j8, k8, l7, l8 k9, l9, m8, m9, n8, n9 vccj u2 u6 vccaux g7, g8, g15, g16, h7, h16, r7, r16, t7, t8, t15, t16 g13, h7, h20, j8, j19, k7, l20, m7, m20, n20, p7, p20, t7, t8, t20, v7, v19, w20, y7, y13 gnd, gnd0-gnd7 a1, a22, ab1, ab22, h8, h15, j9, j10, j11, j12, j13, j14, k9, k10, k11, k12, k13, k14, l9, l10, l11, l12, l13, l14, m9, m10, m11, m12, m13, m14, n9, n10, n11, n12, n13, n14, p9, p10, p11, p12, p13, p14, r8, r15 k10, k11, k12, k13, k14, k15, k16, l10, l11, l12, l13, l14, l15, l16, l17, m10, m11, m12, m13, m14, m15, m16, m17, n10, n11, n12, n13, n14, n15, n16, n17, p10, p11, p12, p13, p14, p15, p16, p17, r10, r11, r12, r13, r14, r15, r16, r17, t10, t11, t12, t13, t14, t15, t16, t17, u10, u11, u12, u13, u14, u15, u16, u17 nc ecp6/ec6: c3, b2, e5, f5, d3, c2, f4, g4, e3, d2, b1, c1, f3, e2, g5, h6, g3, h4, j5, h5, f2, f1, e1, d1, r6, p5, p3, p4, r1, r2, r5, r4, t1, t2, r3, t3, a2, ab2, a21 ecp/ec20: a2, ab2, a21 a25, b2, b23, b24, b25, b26, c2, c3, c19, c20, c21, c22, c23, c24, d3, d5, d20, d21, d22, d24, e5, e19, e21, e22, e24, e25, e26, f4, f5, f20, f22, f23, f24, f26, g5, g20, g26, h2, h3, h5, h6, h22, j2, j3, j7, j21, j22, j23, w5, w7, y5, y6, y19, y20, y21, y22, y23, y24, aa2, aa3, aa4, aa5, aa21, aa22, aa23, aa24, ab3, ab5, ab19, ab20, ab21, ab22, ab23, ab24, ac2, ac3, a c19, ac20, ac21, ac22, ad1, ad2, ad3, ad19, ad20, ad21, ad22, ad23, ad24, ad25, ad26, ae1, ae24, ae25, ae26, af25 4-7 pinout information lattice semiconductor latticeecp/ec family data sheet lfecp6/lfec6 logic signal connections: 144 tqfp pin number pin function bank lvds dual function 1 vccio7 7 2 pl2a 7 t vref2_7 3 pl2b 7 c vref1_7 4 pl7a 7 t 5 pl7b 7 c 6 pl8a 7 t 7 pl8b 7 c 8 pl9a 7 t pclkt7_0 9 pl9b 7 c pclkc7_0 10 xres 6 11 vcc - 12 gnd - 13 vcc - 14 tck 6 15 gnd - 16 tdi 6 17 tms 6 18 tdo 6 19 vccj 6 20 pl20a 6 t llm0_pllt_in_a 21 pl20b 6 c llm0_pllc_in_a 22 pl21a 6 t llm0_pllt_fb_a 23 pl21b 6 c llm0_pllc_fb_a 24 vccio6 6 25 pl22a 6 t 26 pl22b 6 c 27 pl23a 6 t 28 gnd6 6 29 pl23b 6 c 30 pl24a 6 t ldqs24 31 pl24b 6 c 32 pl25a 6 t 33 pl25b 6 c 34 pl27a 6 t vref1_6 35 pl27b 6 c vref2_6 36 vccio6 6 37* gnd5, gnd6 38 vccio5 5 39 pb10a 5 t 40 pb10b 5 c 41 pb11a 5 t 42 pb11b 5 c 43 pb13b 5 4-8 pinout information lattice semiconductor latticeecp/ec family data sheet 44 vccio5 5 45 pb14a 5 t bdqs14 46 pb14b 5 c 47 pb15a 5 t 48 pb15b 5 c 49 pb16a 5 t vref2_5 50 pb16b 5 c vref1_5 51 pb17a 5 t pclkt5_0 52 gnd5 5 53 pb17b 5 c pclkc5_0 54 vccaux - 55 vccio4 4 56 pb18a 4 t writen 57 pb18b 4 c cs1n 58 pb19a 4 t vref1_4 59 pb19b 4 c csn 60 pb20a 4 t vref2_4 61 pb20b 4 c d0/spid7 62 pb21a 4 t d2/spid5 63 gnd4 4 64 pb21b 4 c d1/spid6 65 pb22a 4 t bdqs22 66 pb22b 4 c d3/spid4 67 pb23a 4 t 68 pb23b 4 c d4/spid3 69 pb24b 4 d5/spid2 70 pb25b 4 d6/spid1 71 vccio4 4 72* gnd3, gnd4 73 vccio3 3 74 pr27a 3 vref1_3 75 pr25b 3 c 76 pr25a 3 t 77 pr24b 3 c 78 pr24a 3 t rdqs24 79 pr23b 3 c rlm0_pllc_fb_a 80 gnd3 3 81 pr23a 3 t rlm0_pllt_fb_a 82 pr22b 3 c rlm0_pllc_in_a 83 pr22a 3 t rlm0_pllt_in_a 84 vccio3 3 85 pr21b 3 c di/csspin 86 pr21a 3 t dout/cson 87 pr20b 3 c busy/sispi lfecp6/lfec6 logic signal connections: 144 tqfp (cont.) pin number pin function bank lvds dual function 4-9 pinout information lattice semiconductor latticeecp/ec family data sheet 88 pr20a 3 t d7/spid0 89 cfg2 3 90 cfg1 3 91 cfg0 3 92 vcc - 93 programn 3 94 cclk 3 95 initn 3 96 gnd - 97 done 3 98 gnd - 99 vcc - 100 pr9b 2 c pclkc2_0 101 pr9a 2 t pclkt2_0 102 pr8b 2 c 103 pr8a 2 t 104 pr7b 2 c 105 pr7a 2 t 106 pr2b 2 c vref1_2 107 pr2a 2 t vref2_2 108 vccio2 2 109* gnd1, gnd2 110 vccio1 1 111 pt25b 1 c 112 pt25a 1 t 113 pt23a 1 114 pt22b 1 c 115 pt22a 1 t tdqs22 116 pt21b 1 c 117 gnd1 1 118 pt21a 1 t 119 pt20b 1 c 120 pt20a 1 t 121 pt19b 1 c vref2_1 122 pt19a 1 t vref1_1 123 pt18b 1 c 124 pt18a 1 t 125 vccio1 1 126 vccaux - 127 pt17b 0 c pclkc0_0 128 gnd0 0 129 pt17a 0 t pclkt0_0 130 pt16b 0 c vref1_0 131 pt16a 0 t vref2_0 lfecp6/lfec6 logic signal connections: 144 tqfp (cont.) pin number pin function bank lvds dual function 4-10 pinout information lattice semiconductor latticeecp/ec family data sheet 132 pt15b 0 c 133 pt15a 0 t 134 pt14b 0 c 135 pt14a 0 t tdqs14 136 vccio0 0 137 pt13b 0 c 138 pt13a 0 t 139 pt12b 0 c 140 pt12a 0 t 141 pt10b 0 c 142 pt10a 0 t 143 vccio0 0 144* gnd0, gnd7 * double bonded to the pin. lfecp6/lfec6 logic signal connections: 144 tqfp (cont.) pin number pin function bank lvds dual function 4-11 pinout information lattice semiconductor latticeecp/ec family data sheet lfecp6/lfec6 logic signal connections: 208 pqfp pin number pin function bank lvds dual function 1* gnd0, gnd7 2 vccio7 7 3 pl2a 7 t vref2_7 4 pl2b 7 c vref1_7 5nc - 6nc - 7 pl3b 7 8 pl4a 7 t 9 pl4b 7 c 10 pl5a 7 t 11 pl5b 7 c 12 pl6a 7 t ldqs6 13 vccio7 7 14 pl6b 7 c 15 pl7a 7 t 16 pl7b 7 c 17 pl8a 7 t 18 gnd7 7 19 pl8b 7 c 20 pl9a 7 t pclkt7_0 21 pl9b 7 c pclkc7_0 22 vccaux - 23 xres 6 24 vcc - 25 gnd - 26 vcc - 27 tck 6 28 gnd - 29 tdi 6 30 tms 6 31 tdo 6 32 vccj 6 33 pl20a 6 t llm0_pllt_in_a 34 pl20b 6 c llm0_pllc_in_a 35 pl21a 6 t llm0_pllt_fb_a 36 pl21b 6 c llm0_pllc_fb_a 37 vccio6 6 38 pl22a 6 t 39 pl22b 6 c 40 pl23a 6 t 41 gnd6 6 42 pl23b 6 c 43 pl24a 6 t ldqs24 4-12 pinout information lattice semiconductor latticeecp/ec family data sheet 44 pl24b 6 c 45 pl25a 6 t 46 pl25b 6 c 47 pl26a 6 t 48 pl26b 6 c 49 pl27a 6 t vref1_6 50 pl27b 6 c vref2_6 51 vccio6 6 52* gnd5, gnd6 53 vccio5 5 54 pb2a 5 t 55 pb2b 5 c 56 pb3a 5 t 57 pb3b 5 c 58 pb4a 5 t 59 pb4b 5 c 60 pb5a 5 t 61 pb5b 5 c 62 pb6a 5 t bdqs6 63 pb6b 5 c 64 vccio5 5 65 pb10a 5 t 66 pb10b 5 c 67 pb11a 5 t 68 pb11b 5 c 69 pb12a 5 t 70 pb12b 5 c 71 pb13a 5 t 72 gnd5 5 73 pb13b 5 c 74 vccio5 5 75 pb14a 5 t bdqs14 76 pb14b 5 c 77 pb15a 5 t 78 pb15b 5 c 79 pb16a 5 t vref2_5 80 pb16b 5 c vref1_5 81 pb17a 5 t pclkt5_0 82 gnd5 5 83 pb17b 5 c pclkc5_0 84 vccaux - 85 vccio4 4 86 pb18a 4 t writen 87 pb18b 4 c cs1n lfecp6/lfec6 logic signal connections: 208 pqfp (cont.) pin number pin function bank lvds dual function 4-13 pinout information lattice semiconductor latticeecp/ec family data sheet 88 pb19a 4 t vref1_4 89 pb19b 4 c csn 90 pb20a 4 t vref2_4 91 pb20b 4 c d0/spid7 92 pb21a 4 t d2/spid5 93 gnd4 4 94 pb21b 4 c d1/spid6 95 pb22a 4 t bdqs22 96 pb22b 4 c d3/spid4 97 pb23a 4 t 98 pb23b 4 c d4/spid3 99 pb24a 4 t 100 pb24b 4 c d5/spid2 101 pb25a 4 t 102 pb25b 4 c d6/spid1 103 pb33a 4 104 vccio4 4 105* gnd3, gnd4 106 vccio3 3 107 pr27b 3 c vref2_3 108 pr27a 3 t vref1_3 109 pr26b 3 c 110 pr26a 3 t 111 pr25b 3 c 112 pr25a 3 t 113 pr24b 3 c 114 pr24a 3 t rdqs24 115 pr23b 3 c rlm0_pllc_fb_a 116 gnd3 3 117 pr23a 3 t rlm0_pllt_fb_a 118 pr22b 3 c rlm0_pllc_in_a 119 pr22a 3 t rlm0_pllt_in_a 120 vccio3 3 121 pr21b 3 c di/csspin 122 pr21a 3 t dout/cson 123 pr20b 3 c busy/sispi 124 pr20a 3 t d7/spid0 125 cfg2 3 126 cfg1 3 127 cfg0 3 128 vcc - 129 programn 3 130 cclk 3 131 initn 3 lfecp6/lfec6 logic signal connections: 208 pqfp (cont.) pin number pin function bank lvds dual function 4-14 pinout information lattice semiconductor latticeecp/ec family data sheet 132 gnd - 133 done 3 134 gnd - 135 vcc - 136 vccaux - 137 pr9b 2 c pclkc2_0 138 gnd2 2 139 pr9a 2 t pclkt2_0 140 pr8b 2 c 141 pr8a 2 t 142 pr7b 2 c 143 pr7a 2 t 144 pr6b 2 c 145 vccio2 2 146 pr6a 2 t rdqs6 147 pr5b 2 c 148 pr5a 2 t 149 pr4b 2 c 150 pr4a 2 t 151 nc - 152 nc - 153 pr2b 2 c vref1_2 154 pr2a 2 t vref2_2 155 vccio2 2 156* gnd1, gnd2 157 vccio1 1 158 pt33a 1 159 pt25b 1 c 160 pt25a 1 t 161 pt24b 1 c 162 pt24a 1 t 163 pt23b 1 c 164 pt23a 1 t 165 pt22b 1 c 166 pt22a 1 t tdqs22 167 pt21b 1 c 168 gnd1 1 169 pt21a 1 t 170 pt20b 1 c 171 pt20a 1 t 172 pt19b 1 c vref2_1 173 pt19a 1 t vref1_1 174 pt18b 1 c 175 pt18a 1 t lfecp6/lfec6 logic signal connections: 208 pqfp (cont.) pin number pin function bank lvds dual function 4-15 pinout information lattice semiconductor latticeecp/ec family data sheet 176 vccio1 1 177 vccaux - 178 pt17b 0 c pclkc0_0 179 gnd0 0 180 pt17a 0 t pclkt0_0 181 pt16b 0 c vref1_0 182 pt16a 0 t vref2_0 183 pt15b 0 c 184 pt15a 0 t 185 pt14b 0 c 186 pt14a 0 t tdqs14 187 vccio0 0 188 pt13b 0 c 189 gnd0 0 190 pt13a 0 t 191 pt12b 0 c 192 pt12a 0 t 193 pt11b 0 c 194 pt11a 0 t 195 pt10b 0 c 196 pt10a 0 t 197 vccio0 0 198 pt6b 0 c 199 pt6a 0 t tdqs6 200 pt5b 0 c 201 pt5a 0 t 202 pt4b 0 c 203 pt4a 0 t 204 pt3b 0 c 205 pt3a 0 t 206 pt2b 0 c 207 pt2a 0 t 208 vccio0 0 * double bonded to the pin. lfecp6/lfec6 logic signal connections: 208 pqfp (cont.) pin number pin function bank lvds dual function 4-16 pinout information lattice semiconductor latticeecp/ec family data sheet lfecp6/lfec6 logic signal connections: 256 fpbga ball number ball function bank lvds dual function gnd gnd7 7 d4 pl2a 7 t vref2_7 d3 pl2b 7 c vref1_7 c3 pl3a 7 t c2 pl3b 7 c b1 pl4a 7 t c1 pl4b 7 c e3 pl5a 7 t e4 pl5b 7 c f4 pl6a 7 t ldqs6 f5 pl6b 7 c g4 pl7a 7 t g3 pl7b 7 c d2 pl8a 7 t gnd gnd7 7 d1 pl8b 7 c e1 pl9a 7 t pclkt7_0 e2 pl9b 7 c pclkc7_0 f3 xres 6 g5 pl11a 6 t h5 pl11b 6 c f2 pl12a 6 t f1 pl12b 6 c h4 pl13a 6 t h3 pl13b 6 c g2 pl14a 6 t gnd gnd6 6 g1 pl14b 6 c j4 pl15a 6 t ldqs15 j3 pl15b 6 c j5 pl16a 6 t k5 pl16b 6 c h2 pl17a 6 t h1 pl17b 6 c j2 pl18a 6 t gnd gnd6 6 j1 pl18b 6 c k4 tck 6 k3 tdi 6 l3 tms 6 l5 tdo 6 l4 vccj 6 k2 pl20a 6 t llm0_pllt_in_a 4-17 pinout information lattice semiconductor latticeecp/ec family data sheet k1 pl20b 6 c llm0_pllc_in_a l2 pl21a 6 t llm0_pllt_fb_a l1 pl21b 6 c llm0_pllc_fb_a m2 pl22a 6 t m1 pl22b 6 c n1 pl23a 6 t gnd gnd6 6 n2 pl23b 6 c m4 pl24a 6 t ldqs24 m3 pl24b 6 c p1 pl25a 6 t r1 pl25b 6 c p2 pl26a 6 t p3 pl26b 6 c n3 pl27a 6 t vref1_6 n4 pl27b 6 c vref2_6 gnd gnd6 6 gnd gnd5 5 p4 pb2a 5 t n5 pb2b 5 c p5 pb3a 5 t p6 pb3b 5 c r4 pb4a 5 t r3 pb4b 5 c t2 pb5a 5 t t3 pb5b 5 c r5 pb6a 5 t bdqs6 r6 pb6b 5 c t4 pb7a 5 t t5 pb7b 5 c n6 pb8a 5 t m6 pb8b 5 c t6 pb9a 5 t gnd gnd5 5 t7 pb9b 5 c p7 pb10a 5 t n7 pb10b 5 c r7 pb11a 5 t r8 pb11b 5 c m7 pb12a 5 t m8 pb12b 5 c t8 pb13a 5 t gnd gnd5 5 t9 pb13b 5 c lfecp6/lfec6 logic signal connections: 256 fpbga (cont.) ball number ball function bank lvds dual function 4-18 pinout information lattice semiconductor latticeecp/ec family data sheet p8 pb14a 5 t bdqs14 n8 pb14b 5 c r9 pb15a 5 t r10 pb15b 5 c p9 pb16a 5 t vref2_5 n9 pb16b 5 c vref1_5 t10 pb17a 5 t pclkt5_0 gnd gnd5 5 t11 pb17b 5 c pclkc5_0 t12 pb18a 4 t writen t13 pb18b 4 c cs1n p10 pb19a 4 t vref1_4 n10 pb19b 4 c csn t14 pb20a 4 t vref2_4 t15 pb20b 4 c d0/spid7 m10 pb21a 4 t d2/spid5 gnd gnd4 4 m11 pb21b 4 c d1/spid6 r11 pb22a 4 t bdqs22 p11 pb22b 4 c d3/spid4 r13 pb23a 4 t r14 pb23b 4 c d4/spid3 p12 pb24a 4 t p13 pb24b 4 c d5/spid2 n11 pb25a 4 t gnd gnd4 4 n12 pb25b 4 c d6/spid1 r12 pb26a 4 gnd gnd4 4 gnd gnd4 4 gnd gnd3 3 n13 pr27b 3 c vref2_3 n14 pr27a 3 t vref1_3 p14 pr26b 3 c p15 pr26a 3 t r15 pr25b 3 c r16 pr25a 3 t m13 pr24b 3 c m14 pr24a 3 t rdqs24 p16 pr23b 3 c rlm0_pllc_fb_a gnd gnd3 3 n16 pr23a 3 t rlm0_pllt_fb_a n15 pr22b 3 c rlm0_pllc_in_a m15 pr22a 3 t rlm0_pllt_in_a lfecp6/lfec6 logic signal connections: 256 fpbga (cont.) ball number ball function bank lvds dual function 4-19 pinout information lattice semiconductor latticeecp/ec family data sheet m16 pr21b 3 c di/csspin l16 pr21a 3 t dout/cson k16 pr20b 3 c busy/sispi j16 pr20a 3 t d7/spid0 l12 cfg2 3 l14 cfg1 3 l13 cfg0 3 k13 programn 3 l15 cclk 3 k15 initn 3 k14 done 3 h16 pr18b 3 c gnd gnd3 3 h15 pr18a 3 t g16 pr17b 3 c g15 pr17a 3 t k12 pr16b 3 c j12 pr16a 3 t j14 pr15b 3 c j15 pr15a 3 t rdqs15 f16 pr14b 3 c gnd gnd3 3 f15 pr14a 3 t j13 pr13b 3 c h13 pr13a 3 t h14 pr12b 3 c g14 pr12a 3 t e16 pr11b 3 c e15 pr11a 3 t h12 pr9b 2 c pclkc2_0 gnd gnd2 2 g12 pr9a 2 t pclkt2_0 g13 pr8b 2 c f13 pr8a 2 t f12 pr7b 2 c e13 pr7a 2 t d16 pr6b 2 c d15 pr6a 2 t rdqs6 f14 pr5b 2 c e14 pr5a 2 t c16 pr4b 2 c b16 pr4a 2 t c15 pr3b 2 c c14 pr3a 2 t lfecp6/lfec6 logic signal connections: 256 fpbga (cont.) ball number ball function bank lvds dual function 4-20 pinout information lattice semiconductor latticeecp/ec family data sheet d14 pr2b 2 c vref1_2 d13 pr2a 2 t vref2_2 gnd gnd2 2 gnd gnd1 1 gnd gnd1 1 b13 pt26b 1 c c13 pt26a 1 t gnd gnd1 1 c12 pt25b 1 c d12 pt25a 1 t a15 pt24b 1 c b14 pt24a 1 t d11 pt23b 1 c c11 pt23a 1 t e10 pt22b 1 c e11 pt22a 1 t tdqs22 a14 pt21b 1 c gnd gnd1 1 a13 pt21a 1 t d10 pt20b 1 c c10 pt20a 1 t a12 pt19b 1 c vref2_1 b12 pt19a 1 t vref1_1 a11 pt18b 1 c b11 pt18a 1 t a10 pt17b 0 c pclkc0_0 gnd gnd0 0 b10 pt17a 0 t pclkt0_0 c9 pt16b 0 c vref1_0 b9 pt16a 0 t vref2_0 e9 pt15b 0 c d9 pt15a 0 t d8 pt14b 0 c c8 pt14a 0 t tdqs14 a9 pt13b 0 c gnd gnd0 0 a8 pt13a 0 t b8 pt12b 0 c b7 pt12a 0 t d7 pt11b 0 c c7 pt11a 0 t a7 pt10b 0 c a6 pt10a 0 t e7 pt9b 0 c lfecp6/lfec6 logic signal connections: 256 fpbga (cont.) ball number ball function bank lvds dual function 4-21 pinout information lattice semiconductor latticeecp/ec family data sheet gnd gnd0 0 e6 pt9a 0 t d6 pt8b 0 c c6 pt8a 0 t b6 pt7b 0 c b5 pt7a 0 t a5 pt6b 0 c a4 pt6a 0 t tdqs6 a3 pt5b 0 c a2 pt5a 0 t b2 pt4b 0 c b3 pt4a 0 t d5 pt3b 0 c c5 pt3a 0 t c4 pt2b 0 c b4 pt2a 0 t gnd gnd0 0 a1 gnd - a16 gnd - g10 gnd - g7 gnd - g8 gnd - g9 gnd - h10 gnd - h7 gnd - h8 gnd - h9 gnd - j10 gnd - j7 gnd - j8 gnd - j9 gnd - k10 gnd - k7 gnd - k8 gnd - k9 gnd - t1 gnd - t16 gnd - e12 vcc - e5 vcc - e8 vcc - m12 vcc - m5 vcc - m9 vcc - b15 vccaux - lfecp6/lfec6 logic signal connections: 256 fpbga (cont.) ball number ball function bank lvds dual function 4-22 pinout information lattice semiconductor latticeecp/ec family data sheet r2 vccaux - f7 vccio0 0 f8 vccio0 0 f10 vccio1 1 f9 vccio1 1 g11 vccio2 2 h11 vccio2 2 j11 vccio3 3 k11 vccio3 3 l10 vccio4 4 l9 vccio4 4 l7 vccio5 5 l8 vccio5 5 j6 vccio6 6 k6 vccio6 6 g6 vccio7 7 h6 vccio7 7 f6 vcc - f11 vcc - l11 vcc - l6 vcc - lfecp6/lfec6 logic signal connections: 256 fpbga (cont.) ball number ball function bank lvds dual function 4-23 pinout information lattice semiconductor latticeecp/ec family data sheet lfecp6/lfec6, lfecp20/lfec20 logic signal connections: 484 fpbga lfec6/lfecp6 lfec20/lfecp20 ball number ball function bank lvds dual function ball number ball function bank lvds dual function gnd gnd7 7 gnd gnd7 7 d4 pl2a 7 t vref2_7 d4 pl2a 7 t vref2_7 e4 pl2b 7 c vref1_7 e4 pl2b 7 c vref1_7 c3 nc - c3 pl3a 7 t b2 nc - b2 pl3b 7 c e5 nc - e5 pl4a 7 t f5 nc - f5 pl4b 7 c d3 nc - d3 pl5a 7 t c2 nc - c2 pl5b 7 c f4 nc - f4 pl6a 7 t ldqs6 g4 nc - g4 pl6b 7 c e3 nc - e3 pl7a 7 t d2 nc - d2 pl7b 7 c b1 nc - b1 pl8a 7 t lum0_pllt_in_a c1 nc - c1 pl8b 7 c lum0_pllc_in_a f3 nc - f3 pl9a 7 t lum0_pllt_fb_a -- - gnd gnd7 7 e2 nc - e2 pl9b 7 c lum0_pllc_fb_a g5 nc - g5 pl11a 7 t h6 nc - h6 pl11b 7 c g3 nc - g3 pl12a 7 t h4 nc - h4 pl12b 7 c j5 nc - j5 pl13a 7 t h5 nc - h5 pl13b 7 c f2 nc - f2 pl14a 7 t -- - gnd gnd7 7 f1 nc - f1 pl14b 7 c e1 nc - e1 pl15a 7 t d1 nc - d1 pl15b 7 c h3 pl3a 7 t h3 pl16a 7 t g2 pl3b 7 c g2 pl16b 7 c h2 pl4a 7 t h2 pl17a 7 t g1 pl4b 7 c g1 pl17b 7 c j4 pl5a 7 t j4 pl18a 7 t -- - gnd gnd7 7 j3 pl5b 7 c j3 pl18b 7 c j2 pl6a 7 t ldqs6 j2 pl19a 7 t ldqs19 h1 pl6b 7 c h1 pl19b 7 c k4 pl7a 7 t k4 pl20a 7 t k5 pl7b 7 c k5 pl20b 7 c k3 pl8a 7 t k3 pl21a 7 t k2 pl8b 7 c k2 pl21b 7 c 4-24 pinout information lattice semiconductor latticeecp/ec family data sheet j1 pl9a 7 t pclkt7_0 j1 pl22a 7 t pclkt7_0 gnd gnd7 7 gnd gnd7 7 k1 pl9b 7 c pclkc7_0 k1 pl22b 7 c pclkc7_0 l3 xres 6 l3 xres 6 l4 pl11a 6 t l4 pl24a 6 t l5 pl11b 6 c l5 pl24b 6 c l2 pl12a 6 t l2 pl25a 6 t l1 pl12b 6 c l1 pl25b 6 c m4 pl13a 6 t m4 pl26a 6 t m5 pl13b 6 c m5 pl26b 6 c m1 pl14a 6 t m1 pl27a 6 t gnd gnd6 6 gnd gnd6 6 m2 pl14b 6 c m2 pl27b 6 c n3 pl15a 6 t ldqs15 n3 pl28a 6 t ldqs28 m3 pl15b 6 c m3 pl28b 6 c n5 pl16a 6 t n5 pl29a 6 t n4 pl16b 6 c n4 pl29b 6 c n1 pl17a 6 t n1 pl30a 6 t n2 pl17b 6 c n2 pl30b 6 c p1 pl18a 6 t p1 pl31a 6 t gnd gnd6 6 gnd gnd6 6 p2 pl18b 6 c p2 pl31b 6 c r6 nc - r6 pl32a 6 t p5 nc - p5 pl32b 6 c p3 nc - p3 pl33a 6 t p4 nc - p4 pl33b 6 c r1 nc - r1 pl34a 6 t r2 nc - r2 pl34b 6 c r5 nc - r5 pl35a 6 t -- - gnd gnd6 6 r4 nc - r4 pl35b 6 c t1 nc - t1 pl36a 6 t ldqs36 t2 nc - t2 pl36b 6 c r3 nc - r3 pl37a 6 t t3 nc - t3 pl37b 6 c pl38a 6 t pl38b 6 c pl39a 6 t -- - gnd gnd6 6 pl39b 6 c t5 tck 6 t5 tck 6 u5 tdi 6 u5 tdi 6 lfecp6/lfec6, lfecp20/lfec20 logic signal connections: 484 fpbga lfec6/lfecp6 lfec20/lfecp20 ball number ball function bank lvds dual function ball number ball function bank lvds dual function 4-25 pinout information lattice semiconductor latticeecp/ec family data sheet t4 tms 6 t4 tms 6 u1 tdo 6 u1 tdo 6 u2 vccj 6 u2 vccj 6 v1 pl20a 6 t llm0_pllt_in_a v1 pl41a 6 t llm0_pllt_in_a v2 pl20b 6 c llm0_pllc_in_a v2 pl41b 6 c llm0_pllc_in_a u3 pl21a 6 t llm0_pllt_fb_a u3 pl42a 6 t llm0_pllt_fb_a v3 pl21b 6 c llm0_pllc_fb_a v3 pl42b 6 c llm0_pllc_fb_a u4 pl22a 6 t u4 pl43a 6 t v5 pl22b 6 c v5 pl43b 6 c w1 pl23a 6 t w1 pl44a 6 t gnd gnd6 6 gnd gnd6 6 w2 pl23b 6 c w2 pl44b 6 c y1 pl24a 6 t ldqs24 y1 pl45a 6 t ldqs45 y2 pl24b 6 c y2 pl45b 6 c aa1 pl25a 6 t aa1 pl46a 6 t aa2 pl25b 6 c aa2 pl46b 6 c w4 pl26a 6 t w4 pl47a 6 t v4 pl26b 6 c v4 pl47b 6 c w3 pl27a 6 t vref1_6 w3 pl48a 6 t vref1_6 y3 pl27b 6 c vref2_6 y3 pl48b 6 c vref2_6 gnd gnd6 6 gnd gnd6 6 gnd gnd5 5 gnd gnd5 5 pb2a 5 t pb2b 5 c pb3a 5 t pb3b 5 c pb4a 5 t pb4b 5 c pb5a 5 t pb5b 5 c pb6a 5 t pb6b 5 c pb7a 5 t pb7b 5 c pb8a 5 t pb8b 5 c pb9a 5 t -- - gnd gnd5 5 pb9b 5 c v7 nc - v7 pb10a 5 t t6 nc - t6 pb10b 5 c v8 nc - v8 pb11a 5 t lfecp6/lfec6, lfecp20/lfec20 logic signal connections: 484 fpbga lfec6/lfecp6 lfec20/lfecp20 ball number ball function bank lvds dual function ball number ball function bank lvds dual function 4-26 pinout information lattice semiconductor latticeecp/ec family data sheet u7 nc - u7 pb11b 5 c w5 nc - w5 pb12a 5 t u6 nc - u6 pb12b 5 c aa3 nc - aa3 pb13a 5 t -- - gnd gnd5 5 ab3 nc - ab3 pb13b 5 c y6 nc - y6 pb14a 5 t bdqs14 v6 nc - v6 pb14b 5 c aa5 nc - aa5 pb15a 5 t w6 nc - w6 pb15b 5 c y5 nc - y5 pb16a 5 t y4 nc - y4 pb16b 5 c aa4 nc - aa4 pb17a 5 t -- - gnd gnd5 5 ab4 nc - ab4 pb17b 5 c y7 pb2a 5 t y7 pb18a 5 t w8 pb2b 5 c w8 pb18b 5 c w7 pb3a 5 t w7 pb19a 5 t u8 pb3b 5 c u8 pb19b 5 c w9 pb4a 5 t w9 pb20a 5 t u9 pb4b 5 c u9 pb20b 5 c y8 pb5a 5 t y8 pb21a 5 t -- - gnd gnd5 5 y9 pb5b 5 c y9 pb21b 5 c v9 pb6a 5 t bdqs6 v9 pb22a 5 t bdqs22 t9 pb6b 5 c t9 pb22b 5 c w10 pb7a 5 t w10 pb23a 5 t u10 pb7b 5 c u10 pb23b 5 c v10 pb8a 5 t v10 pb24a 5 t t10 pb8b 5 c t10 pb24b 5 c aa6 pb9a 5 t aa6 pb25a 5 t gnd gnd5 5 gnd gnd5 5 ab5 pb9b 5 c ab5 pb25b 5 c aa8 pb10a 5 t aa8 pb26a 5 t aa7 pb10b 5 c aa7 pb26b 5 c ab6 pb11a 5 t ab6 pb27a 5 t ab7 pb11b 5 c ab7 pb27b 5 c y10 pb12a 5 t y10 pb28a 5 t w11 pb12b 5 c w11 pb28b 5 c ab8 pb13a 5 t ab8 pb29a 5 t gnd gnd5 5 gnd gnd5 5 ab9 pb13b 5 c ab9 pb29b 5 c lfecp6/lfec6, lfecp20/lfec20 logic signal connections: 484 fpbga lfec6/lfecp6 lfec20/lfecp20 ball number ball function bank lvds dual function ball number ball function bank lvds dual function 4-27 pinout information lattice semiconductor latticeecp/ec family data sheet aa10 pb14a 5 t bdqs14 aa10 pb30a 5 t bdqs30 aa9 pb14b 5 c aa9 pb30b 5 c y11 pb15a 5 t y11 pb31a 5 t aa11 pb15b 5 c aa11 pb31b 5 c v11 pb16a 5 t vref2_5 v11 pb32a 5 t vref2_5 v12 pb16b 5 c vref1_5 v12 pb32b 5 c vref1_5 ab10 pb17a 5 t pclkt5_0 ab10 pb33a 5 t pclkt5_0 gnd gnd5 5 gnd gnd5 5 ab11 pb17b 5 c pclkc5_0 ab11 pb33b 5 c pclkc5_0 y12 pb18a 4 t writen y12 pb34a 4 t writen u11 pb18b 4 c cs1n u11 pb34b 4 c cs1n w12 pb19a 4 t vref1_4 w12 pb35a 4 t vref1_4 u12 pb19b 4 c csn u12 pb35b 4 c csn w13 pb20a 4 t vref2_4 w13 pb36a 4 t vref2_4 u13 pb20b 4 c d0/spid7 u13 pb36b 4 c d0/spid7 aa12 pb21a 4 t d2/spid5 aa12 pb37a 4 t d2/spid5 gnd gnd4 4 gnd gnd4 4 ab12 pb21b 4 c d1/spid6 ab12 pb37b 4 c d1/spid6 t13 pb22a 4 t bdqs22 t13 pb38a 4 t bdqs38 v13 pb22b 4 c d3/spid4 v13 pb38b 4 c d3/spid4 w14 pb23a 4 t w14 pb39a 4 t u14 pb23b 4 c d4/spid3 u14 pb39b 4 c d4/spid3 y13 pb24a 4 t y13 pb40a 4 t v14 pb24b 4 c d5/spid2 v14 pb40b 4 c d5/spid2 aa13 pb25a 4 t aa13 pb41a 4 t gnd gnd4 4 gnd gnd4 4 ab13 pb25b 4 c d6/spid1 ab13 pb41b 4 c d6/spid1 aa14 pb26a 4 t aa14 pb42a 4 t y14 pb26b 4 c y14 pb42b 4 c y15 pb27a 4 t y15 pb43a 4 t w15 pb27b 4 c w15 pb43b 4 c v15 pb28a 4 t v15 pb44a 4 t t14 pb28b 4 c t14 pb44b 4 c ab14 pb29a 4 t ab14 pb45a 4 t gnd gnd4 4 gnd gnd4 4 ab15 pb29b 4 c ab15 pb45b 4 c ab16 pb30a 4 t bdqs30 ab16 pb46a 4 t bdqs46 aa15 pb30b 4 c aa15 pb46b 4 c ab17 pb31a 4 t ab17 pb47a 4 t aa16 pb31b 4 c aa16 pb47b 4 c ab18 pb32a 4 t ab18 pb48a 4 t aa17 pb32b 4 c aa17 pb48b 4 c lfecp6/lfec6, lfecp20/lfec20 logic signal connections: 484 fpbga lfec6/lfecp6 lfec20/lfecp20 ball number ball function bank lvds dual function ball number ball function bank lvds dual function 4-28 pinout information lattice semiconductor latticeecp/ec family data sheet ab19 pb33a 4 t ab19 pb49a 4 t -- - gnd gnd4 4 aa18 pb33b 4 c aa18 pb49b 4 c w16 nc - w16 pb50a 4 t u15 nc - u15 pb50b 4 c v16 nc - v16 pb51a 4 t u16 nc - u16 pb51b 4 c y17 nc - y17 pb52a 4 t v17 nc - v17 pb52b 4 c ab20 nc - ab20 pb53a 4 t -- - gnd gnd4 4 aa19 nc - aa19 pb53b 4 c y16 nc - y16 pb54a 4 t bdqs54 w17 nc - w17 pb54b 4 c aa20 nc - aa20 pb55a 4 t y19 nc - y19 pb55b 4 c y18 nc - y18 pb56a 4 t w18 nc - w18 pb56b 4 c t17 nc - t17 pb57a 4 t u17 nc - u17 pb57b 4 c gnd gnd4 4 gnd gnd4 4 gnd gnd3 3 gnd gnd3 3 w20 pr27b 3 c vref2_3 w20 pr48b 3 c vref2_3 y20 pr27a 3 t vref1_3 y20 pr48a 3 t vref1_3 aa21 pr26b 3 c aa21 pr47b 3 c ab21 pr26a 3 t ab21 pr47a 3 t w19 pr25b 3 c w19 pr46b 3 c v19 pr25a 3 t v19 pr46a 3 t y21 pr24b 3 c y21 pr45b 3 c aa22 pr24a 3 t rdqs24 aa22 pr45a 3 t rdqs45 v20 pr23b 3 c rlm0_pllc_fb_a v20 pr44b 3 c rlm0_pllc_in_a gnd gnd3 3 gnd gnd3 3 u20 pr23a 3 t rlm0_pllt_fb_a u20 pr44a 3 t rlm0_pllt_in_a w21 pr22b 3 c rlm0_pllc_in_a w21 pr43b 3 c rlm0_pllc_fb_a y22 pr22a 3 t rlm0_pllt_in_a y22 pr43a 3 t rlm0_pllt_fb_a v21 pr21b 3 c di/csspin v21 pr42b 3 c di/csspin w22 pr21a 3 t dout/cson w22 pr42a 3 t dout/cson u21 pr20b 3 c busy/sispi u21 pr41b 3 c busy/sispi v22 pr20a 3 t d7/spid0 v22 pr41a 3 t d7/spid0 t19 cfg2 3 t19 cfg2 3 u19 cfg1 3 u19 cfg1 3 u18 cfg0 3 u18 cfg0 3 lfecp6/lfec6, lfecp20/lfec20 logic signal connections: 484 fpbga lfec6/lfecp6 lfec20/lfecp20 ball number ball function bank lvds dual function ball number ball function bank lvds dual function 4-29 pinout information lattice semiconductor latticeecp/ec family data sheet v18 pro- gramn 3 v18 pro- gramn 3 t20 cclk 3 t20 cclk 3 t21 initn 3 t21 initn 3 r20 done 3 r20 done 3 pr39b 3 c -- - gnd gnd3 3 pr39a 3 t pr38b 3 c pr38a 3 t t18 nc - t18 pr37b 3 c r17 nc - r17 pr37a 3 t r19 nc - r19 pr36b 3 c r18 nc - r18 pr36a 3 t rdqs36 u22 nc - u22 pr35b 3 c -- - gnd gnd3 3 t22 nc - t22 pr35a 3 t r21 nc - r21 pr34b 3 c r22 nc - r22 pr34a 3 t p20 nc - p20 pr33b 3 c n20 nc - n20 pr33a 3 t p19 nc - p19 pr32b 3 c p18 nc - p18 pr32a 3 t p21 pr18b 3 c p21 pr31b 3 c gnd gnd3 3 gnd gnd3 3 p22 pr18a 3 t p22 pr31a 3 t n21 pr17b 3 c n21 pr30b 3 c n22 pr17a 3 t n22 pr30a 3 t n19 pr16b 3 c n19 pr29b 3 c n18 pr16a 3 t n18 pr29a 3 t m21 pr15b 3 c m21 pr28b 3 c l20 pr15a 3 t rdqs15 l20 pr28a 3 t rdqs28 l21 pr14b 3 c l21 pr27b 3 c gnd gnd3 3 gnd gnd3 3 m20 pr14a 3 t m20 pr27a 3 t m18 pr13b 3 c m18 pr26b 3 c m19 pr13a 3 t m19 pr26a 3 t m22 pr12b 3 c m22 pr25b 3 c l22 pr12a 3 t l22 pr25a 3 t k22 pr11b 3 c k22 pr24b 3 c k21 pr11a 3 t k21 pr24a 3 t j22 pr9b 2 c pclkc2_0 j22 pr22b 2 c pclkc2_0 lfecp6/lfec6, lfecp20/lfec20 logic signal connections: 484 fpbga lfec6/lfecp6 lfec20/lfecp20 ball number ball function bank lvds dual function ball number ball function bank lvds dual function 4-30 pinout information lattice semiconductor latticeecp/ec family data sheet gnd gnd2 2 gnd gnd2 2 j21 pr9a 2 t pclkt2_0 j21 pr22a 2 t pclkt2_0 h22 pr8b 2 c h22 pr21b 2 c h21 pr8a 2 t h21 pr21a 2 t l19 pr7b 2 c l19 pr20b 2 c l18 pr7a 2 t l18 pr20a 2 t k20 pr6b 2 c k20 pr19b 2 c j20 pr6a 2 t rdqs6 j20 pr19a 2 t rdqs19 k19 pr5b 2 c k19 pr18b 2 c -- - gnd gnd2 2 k18 pr5a 2 t k18 pr18a 2 t g22 pr4b 2 c g22 pr17b 2 c f22 pr4a 2 t f22 pr17a 2 t f21 pr3b 2 c f21 pr16b 2 c e22 pr3a 2 t e22 pr16a 2 t e21 nc - e21 pr15b 2 c d22 nc - d22 pr15a 2 t g21 nc - g21 pr14b 2 c g20 nc - g20 pr14a 2 t -- - gnd gnd2 2 j18 nc - j18 pr13b 2 c h19 nc - h19 pr13a 2 t j19 nc - j19 pr12b 2 c h20 nc - h20 pr12a 2 t h17 nc - h17 pr11b 2 c h18 nc - h18 pr11a 2 t d21 nc - d21 pr9b 2 c rum0_pllc_fb_a -- - gnd gnd2 2 c22 nc - c22 pr9a 2 t rum0_pllt_fb_a g19 nc - g19 pr8b 2 c rum0_pllc_in_a g18 nc - g18 pr8a 2 t rum0_pllt_in_a f20 nc - f20 pr7b 2 c f19 nc - f19 pr7a 2 t e20 nc - e20 pr6b 2 c d20 nc - d20 pr6a 2 t rdqs6 c21 nc - c21 pr5b 2 c c20 nc - c20 pr5a 2 t f18 nc - f18 pr4b 2 c e18 nc - e18 pr4a 2 t b22 nc - b22 pr3b 2 c b21 nc - b21 pr3a 2 t e19 pr2b 2 c vref1_2 e19 pr2b 2 c vref1_2 lfecp6/lfec6, lfecp20/lfec20 logic signal connections: 484 fpbga lfec6/lfecp6 lfec20/lfecp20 ball number ball function bank lvds dual function ball number ball function bank lvds dual function 4-31 pinout information lattice semiconductor latticeecp/ec family data sheet d19 pr2a 2 t vref2_2 d19 pr2a 2 t vref2_2 gnd gnd2 2 gnd gnd2 2 gnd gnd1 1 gnd gnd1 1 g17 nc - g17 pt57b 1 c f17 nc - f17 pt57a 1 t d18 nc - d18 pt56b 1 c c18 nc - c18 pt56a 1 t c19 nc - c19 pt55b 1 c b20 nc - b20 pt55a 1 t d17 nc - d17 pt54b 1 c c16 nc - c16 pt54a 1 t tdqs54 b19 nc - b19 pt53b 1 c -- - gnd gnd1 1 a20 nc - a20 pt53a 1 t e17 nc - e17 pt52b 1 c c17 nc - c17 pt52a 1 t f16 nc - f16 pt51b 1 c e16 nc - e16 pt51a 1 t f15 nc - f15 pt50b 1 c d16 nc - d16 pt50a 1 t b18 pt33b 1 c b18 pt49b 1 c -- - gnd gnd1 1 a19 pt33a 1 t a19 pt49a 1 t b17 pt32b 1 c b17 pt48b 1 c a18 pt32a 1 t a18 pt48a 1 t b16 pt31b 1 c b16 pt47b 1 c a17 pt31a 1 t a17 pt47a 1 t b15 pt30b 1 c b15 pt46b 1 c a16 pt30a 1 t tdqs30 a16 pt46a 1 t tdqs46 a15 pt29b 1 c a15 pt45b 1 c gnd gnd1 1 gnd gnd1 1 a14 pt29a 1 t a14 pt45a 1 t g14 pt28b 1 c g14 pt44b 1 c e15 pt28a 1 t e15 pt44a 1 t d15 pt27b 1 c d15 pt43b 1 c c15 pt27a 1 t c15 pt43a 1 t c14 pt26b 1 c c14 pt42b 1 c b14 pt26a 1 t b14 pt42a 1 t a13 pt25b 1 c a13 pt41b 1 c gnd gnd1 1 gnd gnd1 1 b13 pt25a 1 t b13 pt41a 1 t e14 pt24b 1 c e14 pt40b 1 c lfecp6/lfec6, lfecp20/lfec20 logic signal connections: 484 fpbga lfec6/lfecp6 lfec20/lfecp20 ball number ball function bank lvds dual function ball number ball function bank lvds dual function 4-32 pinout information lattice semiconductor latticeecp/ec family data sheet c13 pt24a 1 t c13 pt40a 1 t f14 pt23b 1 c f14 pt39b 1 c d14 pt23a 1 t d14 pt39a 1 t e13 pt22b 1 c e13 pt38b 1 c g13 pt22a 1 t tdqs22 g13 pt38a 1 t tdqs38 a12 pt21b 1 c a12 pt37b 1 c gnd gnd1 1 gnd gnd1 1 b12 pt21a 1 t b12 pt37a 1 t f13 pt20b 1 c f13 pt36b 1 c d13 pt20a 1 t d13 pt36a 1 t f12 pt19b 1 c vref2_1 f12 pt35b 1 c vref2_1 d12 pt19a 1 t vref1_1 d12 pt35a 1 t vref1_1 f11 pt18b 1 c f11 pt34b 1 c c12 pt18a 1 t c12 pt34a 1 t a11 pt17b 0 c pclkc0_0 a11 pt33b 0 c pclkc0_0 gnd gnd0 0 gnd gnd0 0 a10 pt17a 0 t pclkt0_0 a10 pt33a 0 t pclkt0_0 e12 pt16b 0 c vref1_0 e12 pt32b 0 c vref1_0 e11 pt16a 0 t vref2_0 e11 pt32a 0 t vref2_0 b11 pt15b 0 c b11 pt31b 0 c c11 pt15a 0 t c11 pt31a 0 t b9 pt14b 0 c b9 pt30b 0 c b10 pt14a 0 t tdqs14 b10 pt30a 0 t tdqs30 a9 pt13b 0 c a9 pt29b 0 c gnd gnd0 0 gnd gnd0 0 a8 pt13a 0 t a8 pt29a 0 t d11 pt12b 0 c d11 pt28b 0 c c10 pt12a 0 t c10 pt28a 0 t a7 pt11b 0 c a7 pt27b 0 c a6 pt11a 0 t a6 pt27a 0 t b7 pt10b 0 c b7 pt26b 0 c b8 pt10a 0 t b8 pt26a 0 t a5 pt9b 0 c a5 pt25b 0 c gnd gnd0 0 gnd gnd0 0 b6 pt9a 0 t b6 pt25a 0 t g10 pt8b 0 c g10 pt24b 0 c e10 pt8a 0 t e10 pt24a 0 t f10 pt7b 0 c f10 pt23b 0 c d10 pt7a 0 t d10 pt23a 0 t g9 pt6b 0 c g9 pt22b 0 c e9 pt6a 0 t tdqs6 e9 pt22a 0 t tdqs22 c9 pt5b 0 c c9 pt21b 0 c lfecp6/lfec6, lfecp20/lfec20 logic signal connections: 484 fpbga lfec6/lfecp6 lfec20/lfecp20 ball number ball function bank lvds dual function ball number ball function bank lvds dual function 4-33 pinout information lattice semiconductor latticeecp/ec family data sheet -- - gnd gnd0 0 c8 pt5a 0 t c8 pt21a 0 t f9 pt4b 0 c f9 pt20b 0 c d9 pt4a 0 t d9 pt20a 0 t f8 pt3b 0 c f8 pt19b 0 c d7 pt3a 0 t d7 pt19a 0 t d8 pt2b 0 c d8 pt18b 0 c c7 pt2a 0 t c7 pt18a 0 t gnd gnd0 0 gnd gnd0 0 a4 nc - a4 pt17b 0 c b4 nc - b4 pt17a 0 t c4 nc - c4 pt16b 0 c c5 nc - c5 pt16a 0 t d6 nc - d6 pt15b 0 c b5 nc - b5 pt15a 0 t e6 nc - e6 pt14b 0 c c6 nc - c6 pt14a 0 t tdqs14 a3 nc - a3 pt13b 0 c -- - gnd gnd0 0 b3 nc - b3 pt13a 0 t f6 nc - f6 pt12b 0 c d5 nc - d5 pt12a 0 t f7 nc - f7 pt11b 0 c e8 nc - e8 pt11a 0 t g6 nc - g6 pt10b 0 c e7 nc - e7 pt10a 0 t pr9b c -- - gnd gnd0 0 pt9a 0 t pr8b 0 c pt8a 0 t pt7b 0 c pt7a 0 t pt6a 0 c pt6a 0 t pt5b 0 c pt5a 0 t pt4b 0 c pt4a 0 t pt3b 0 c pt3a 0 t pt2b 0 c lfecp6/lfec6, lfecp20/lfec20 logic signal connections: 484 fpbga lfec6/lfecp6 lfec20/lfecp20 ball number ball function bank lvds dual function ball number ball function bank lvds dual function 4-34 pinout information lattice semiconductor latticeecp/ec family data sheet pt2a 0 t -- - gnd gnd0 a1 gnd - a1 gnd - a22 gnd - a22 gnd - ab1 gnd - ab1 gnd - ab22 gnd - ab22 gnd - h15 gnd - h15 gnd - h8 gnd - h8 gnd - j10 gnd - j10 gnd - j11 gnd - j11 gnd - j12 gnd - j12 gnd - j13 gnd - j13 gnd - j14 gnd - j14 gnd - j9 gnd - j9 gnd - k10 gnd - k10 gnd - k11 gnd - k11 gnd - k12 gnd - k12 gnd - k13 gnd - k13 gnd - k14 gnd - k14 gnd - k9 gnd - k9 gnd - l10 gnd - l10 gnd - l11 gnd - l11 gnd - l12 gnd - l12 gnd - l13 gnd - l13 gnd - l14 gnd - l14 gnd - l9 gnd - l9 gnd - m10 gnd - m10 gnd - m11 gnd - m11 gnd - m12 gnd - m12 gnd - m13 gnd - m13 gnd - m14 gnd - m14 gnd - m9 gnd - m9 gnd - n10 gnd - n10 gnd - n11 gnd - n11 gnd - n12 gnd - n12 gnd - n13 gnd - n13 gnd - n14 gnd - n14 gnd - n9 gnd - n9 gnd - p10 gnd - p10 gnd - p11 gnd - p11 gnd - p12 gnd - p12 gnd - p13 gnd - p13 gnd - lfecp6/lfec6, lfecp20/lfec20 logic signal connections: 484 fpbga lfec6/lfecp6 lfec20/lfecp20 ball number ball function bank lvds dual function ball number ball function bank lvds dual function 4-35 pinout information lattice semiconductor latticeecp/ec family data sheet p14 gnd - p14 gnd - p9 gnd - p9 gnd - r15 gnd - r15 gnd - r8 gnd - r8 gnd - j16 vcc - j16 vcc - j7 vcc - j7 vcc - k16 vcc - k16 vcc - k17 vcc - k17 vcc - k6 vcc - k6 vcc - k7 vcc - k7 vcc - l17 vcc - l17 vcc - l6 vcc - l6 vcc - m17 vcc - m17 vcc - m6 vcc - m6 vcc - n16 vcc - n16 vcc - n17 vcc - n17 vcc - n6 vcc - n6 vcc - n7 vcc - n7 vcc - p16 vcc - p16 vcc - p7 vcc - p7 vcc - g11 vccio0 0 g11 vccio0 0 h10 vccio0 0 h10 vccio0 0 h11 vccio0 0 h11 vccio0 0 h9 vccio0 0 h9 vccio0 0 g12 vccio1 1 g12 vccio1 1 h12 vccio1 1 h12 vccio1 1 h13 vccio1 1 h13 vccio1 1 h14 vccio1 1 h14 vccio1 1 j15 vccio2 2 j15 vccio2 2 k15 vccio2 2 k15 vccio2 2 l15 vccio2 2 l15 vccio2 2 l16 vccio2 2 l16 vccio2 2 m15 vccio3 3 m15 vccio3 3 m16 vccio3 3 m16 vccio3 3 n15 vccio3 3 n15 vccio3 3 p15 vccio3 3 p15 vccio3 3 r12 vccio4 4 r12 vccio4 4 r13 vccio4 4 r13 vccio4 4 r14 vccio4 4 r14 vccio4 4 t12 vccio4 4 t12 vccio4 4 r10 vccio5 5 r10 vccio5 5 r11 vccio5 5 r11 vccio5 5 lfecp6/lfec6, lfecp20/lfec20 logic signal connections: 484 fpbga lfec6/lfecp6 lfec20/lfecp20 ball number ball function bank lvds dual function ball number ball function bank lvds dual function 4-36 pinout information lattice semiconductor latticeecp/ec family data sheet r9 vccio5 5 r9 vccio5 5 t11 vccio5 5 t11 vccio5 5 m7 vccio6 6 m7 vccio6 6 m8 vccio6 6 m8 vccio6 6 n8 vccio6 6 n8 vccio6 6 p8 vccio6 6 p8 vccio6 6 j8 vccio7 7 j8 vccio7 7 k8 vccio7 7 k8 vccio7 7 l7 vccio7 7 l7 vccio7 7 l8 vccio7 7 l8 vccio7 7 g15 vccaux - g15 vccaux - g16 vccaux - g16 vccaux - g7 vccaux - g7 vccaux - g8 vccaux - g8 vccaux - h16 vccaux - h16 vccaux - h7 vccaux - h7 vccaux - r16 vccaux - r16 vccaux - r7 vccaux - r7 vccaux - t15 vccaux - t15 vccaux - t16 vccaux - t16 vccaux - t7 vccaux - t7 vccaux - t8 vccaux - t8 vccaux - j6 vcc - j6 vcc - j17 vcc - j17 vcc - p6 vcc - p6 vcc - p17 vcc - p17 vcc - a2 nc - a2 nc - ab2 nc - ab2 nc - a21 nc - a21 nc - lfecp6/lfec6, lfecp20/lfec20 logic signal connections: 484 fpbga lfec6/lfecp6 lfec20/lfecp20 ball number ball function bank lvds dual function ball number ball function bank lvds dual function 4-37 pinout information lattice semiconductor latticeecp/ec family data sheet lfecp20/lfec20 logic signal connections: 672 fpbga ball number ball function bank lvds dual function e3 pl2a 7 t vref2_7 e4 pl2b 7 c vref1_7 b1 pl3a 7 t c1 pl3b 7 c f3 pl4a 7 t g3 pl4b 7 c d2 pl5a 7 t e2 pl5b 7 c d1 pl6a 7 t ldqs6 e1 pl6b 7 c f2 pl7a 7 t g2 pl7b 7 c f6 pl8a 7 t lum0_pllt_in_a g6 pl8b 7 c lum0_pllc_in_a h4 pl9a 7 t lum0_pllt_fb_a gnd gnd07 g4 pl9b 7 c lum0_pllc_fb_a j4 pl11a 7 t j5 pl11b 7 c k4 pl12a 7 t k5 pl12b 7 c j6 pl13a 7 t k6 pl13b 7 c f1 pl14a 7 t gnd gnd07 g1 pl14b 7 c h1 pl15a 7 t j1 pl15b 7 c k2 pl16a 7 t k1 pl16b 7 c k3 pl17a 7 t l3 pl17b 7 c l2 pl18a 7 t gnd gnd07 l1 pl18b 7 c m3 pl19a 7 t ldqs19 m4 pl19b 7 c m1 pl20a 7 t m2 pl20b 7 c l4 pl21a 7 t l5 pl21b 7 c n2 pl22a 7 t pclkt7_0 gnd gnd07 4-38 pinout information lattice semiconductor latticeecp/ec family data sheet n1 pl22b 7 c pclkc7_0 n3 xres 6 p1 pl24a 6 t p2 pl24b 6 c l7 pl25a 6 t l6 pl25b 6 c n4 pl26a 6 t n5 pl26b 6 c r1 pl27a 6 t gnd gnd06 r2 pl27b 6 c p4 pl28a 6 t ldqs28 p3 pl28b 6 c m5 pl29a 6 t m6 pl29b 6 c t1 pl30a 6 t t2 pl30b 6 c r4 pl31a 6 t gnd gnd06 r3 pl31b 6 c n6 pl32a 6 t p5 pl32b 6 c p6 pl33a 6 t r5 pl33b 6 c u1 pl34a 6 t u2 pl34b 6 c t3 pl35a 6 t gnd gnd06 t4 pl35b 6 c r6 pl36a 6 t ldqs36 t5 pl36b 6 c t6 pl37a 6 t u5 pl37b 6 c u3 pl38a 6 t u4 pl38b 6 c v1 pl39a 6 t gnd gnd06 v2 pl39b 6 c u7 tck 6 v4 tdi 6 v5 tms 6 v3 tdo 6 u6 vccj 6 w1 pl41a 6 t llm0_pllt_in_a lfecp20/lfec20 logic signal connections: 672 fpbga (cont.) ball number ball function bank lvds dual function 4-39 pinout information lattice semiconductor latticeecp/ec family data sheet w2 pl41b 6 c llm0_pllc_in_a v6 pl42a 6 t llm0_pllt_fb_a w6 pl42b 6 c llm0_pllc_fb_a y1 pl43a 6 t y2 pl43b 6 c w3 pl44a 6 t gnd gnd06 w4 pl44b 6 c aa1 pl45a 6 t ldqs45 ab1 pl45b 6 c y4 pl46a 6 t y3 pl46b 6 c ac 1 pl47a 6 t ab2 pl47b 6 c ab4 pl48a 6 t vref1_6 ac 4 pl48b 6 c vref2_6 gnd gnd06 gnd gnd05 ab6 pb2a 5 t aa6 pb2b 5 c ac 7 pb3a 5 t y8 pb3b 5 c ab7 pb4a 5 t aa7 pb4b 5 c ac 6 pb5a 5 t ac 5 pb5b 5 c ab8 pb6a 5 t bdqs6 ac 8 pb6b 5 c ae2 pb7a 5 t aa8 pb7b 5 c af2 pb8a 5 t y9 pb8b 5 c ad5 pb9a 5 t gnd gnd05 ad4 pb9b 5 c ad8 pb10a 5 t ac 9 pb10b 5 c ae3 pb11a 5 t ab9 pb11b 5 c af3 pb12a 5 t ad9 pb12b 5 c ae4 pb13a 5 t gnd gnd05 af4 pb13b 5 c lfecp20/lfec20 logic signal connections: 672 fpbga (cont.) ball number ball function bank lvds dual function 4-40 pinout information lattice semiconductor latticeecp/ec family data sheet ae5 pb14a 5 t bdqs14 aa9 pb14b 5 c af5 pb15a 5 t y10 pb15b 5 c ad6 pb16a 5 t a c10 pb16b 5 c af6 pb17a 5 t gnd gnd05 ae6 pb17b 5 c af7 pb18a 5 t ab10 pb18b 5 c ae7 pb19a 5 t ad10 pb19b 5 c ad7 pb20a 5 t aa10 pb20b 5 c af8 pb21a 5 t gnd gnd05 af9 pb21b 5 c ad11 pb22a 5 t bdqs22 y11 pb22b 5 c ae8 pb23a 5 t a c11 pb23b 5 c af10 pb24a 5 t ab11 pb24b 5 c ae10 pb25a 5 t gnd gnd05 ae9 pb25b 5 c aa11 pb26a 5 t y12 pb26b 5 c ae11 pb27a 5 t af11 pb27b 5 c af12 pb28a 5 t ae12 pb28b 5 c ad12 pb29a 5 t gnd gnd05 a c12 pb29b 5 c aa12 pb30a 5 t bdqs30 ab12 pb30b 5 c ae13 pb31a 5 t af13 pb31b 5 c ad13 pb32a 5 t vref2_5 a c13 pb32b 5 c vref1_5 af14 pb33a 5 t pclkt5_0 gnd gnd05 lfecp20/lfec20 logic signal connections: 672 fpbga (cont.) ball number ball function bank lvds dual function 4-41 pinout information lattice semiconductor latticeecp/ec family data sheet ae14 pb33b 5 c pclkc5_0 aa13 pb34a 4 t writen ab13 pb34b 4 c cs1n ad14 pb35a 4 t vref1_4 aa14 pb35b 4 c csn a c14 pb36a 4 t vref2_4 ab14 pb36b 4 c d0/spid7 af15 pb37a 4 t d2/spid5 gnd gnd04 ae15 pb37b 4 c d1/spid6 ad15 pb38a 4 t bdqs38 a c15 pb38b 4 c d3/spid4 af16 pb39a 4 t y14 pb39b 4 c d4/spid3 ae16 pb40a 4 t ab15 pb40b 4 c d5/spid2 af17 pb41a 4 t gnd gnd04 ae17 pb41b 4 c d6/spid1 y15 pb42a 4 t aa15 pb42b 4 c ad17 pb43a 4 t y16 pb43b 4 c ad18 pb44a 4 t a c16 pb44b 4 c ae18 pb45a 4 t gnd gnd04 af18 pb45b 4 c ad16 pb46a 4 t bdqs46 ab16 pb46b 4 c af19 pb47a 4 t aa16 pb47b 4 c aa17 pb48a 4 t y17 pb48b 4 c af21 pb49a 4 t gnd gnd04 af20 pb49b 4 c ae21 pb50a 4 t a c17 pb50b 4 c af22 pb51a 4 t ab17 pb51b 4 c ae22 pb52a 4 t aa18 pb52b 4 c ae19 pb53a 4 t lfecp20/lfec20 logic signal connections: 672 fpbga (cont.) ball number ball function bank lvds dual function 4-42 pinout information lattice semiconductor latticeecp/ec family data sheet gnd gnd04 ae20 pb53b 4 c aa19 pb54a 4 t bdqs54 y18 pb54b 4 c af23 pb55a 4 t aa20 pb55b 4 c a c18 pb56a 4 t ab18 pb56b 4 c af24 pb57a 4 t ae23 pb57b 4 c gnd gnd04 gnd gnd03 a c23 pr48b 3 c vref2_3 a c24 pr48a 3 t vref1_3 a c25 pr47b 3 c a c26 pr47a 3 t ab25 pr46b 3 c aa25 pr46a 3 t ab26 pr45b 3 c aa26 pr45a 3 t rdqs45 w23 pr44b 3 c rlm0_pllc_in_a gnd gnd03 w24 pr44a 3 t rlm0_pllt_in_a w22 pr43b 3 c rlm0_pllc_fb_a w21 pr43a 3 t rlm0_pllt_fb_a y25 pr42b 3 c di/csspin y26 pr42a 3 t dout/cson w25 pr41b 3 c busy/sispi w26 pr41a 3 t d7/spid0 v24 cfg2 3 v21 cfg1 3 v23 cfg0 3 v22 programn 3 v20 cclk 3 v25 initn 3 u20 done 3 v26 pr39b 3 c gnd gnd03 u26 pr39a 3 t u24 pr38b 3 c u25 pr38a 3 t u23 pr37b 3 c u22 pr37a 3 t u21 pr36b 3 c lfecp20/lfec20 logic signal connections: 672 fpbga (cont.) ball number ball function bank lvds dual function 4-43 pinout information lattice semiconductor latticeecp/ec family data sheet t21 pr36a 3 t rdqs36 t25 pr35b 3 c gnd gnd03 t26 pr35a 3 t t22 pr34b 3 c t23 pr34a 3 t t24 pr33b 3 c r23 pr33a 3 t r25 pr32b 3 c r24 pr32a 3 t r26 pr31b 3 c gnd gnd03 p26 pr31a 3 t r21 pr30b 3 c r22 pr30a 3 t p25 pr29b 3 c p24 pr29a 3 t p23 pr28b 3 c p22 pr28a 3 t rdqs28 n26 pr27b 3 c gnd gnd03 m26 pr27a 3 t n21 pr26b 3 c p21 pr26a 3 t n23 pr25b 3 c n22 pr25a 3 t n25 pr24b 3 c n24 pr24a 3 t l26 pr22b 2 c pclkc2_0 gnd gnd02 k26 pr22a 2 t pclkt2_0 m22 pr21b 2 c m23 pr21a 2 t m25 pr20b 2 c m24 pr20a 2 t m21 pr19b 2 c l21 pr19a 2 t rdqs19 l22 pr18b 2 c gnd gnd02 l23 pr18a 2 t l25 pr17b 2 c l24 pr17a 2 t k25 pr16b 2 c j25 pr16a 2 t lfecp20/lfec20 logic signal connections: 672 fpbga (cont.) ball number ball function bank lvds dual function 4-44 pinout information lattice semiconductor latticeecp/ec family data sheet j26 pr15b 2 c h26 pr15a 2 t h25 pr14b 2 c j24 pr14a 2 t gnd gnd02 k21 pr13b 2 c k22 pr13a 2 t k20 pr12b 2 c j20 pr12a 2 t k23 pr11b 2 c k24 pr11a 2 t f25 pr9b 2 c r um0_pllc_fb_a gnd gnd02 g25 pr9a 2 t rum0_pllt_fb_a h23 pr8b 2 c rum0_pllc_in_a h24 pr8a 2 t rum0_pllt_in_a h21 pr7b 2 c g21 pr7a 2 t d26 pr6b 2 c d25 pr6a 2 t rdqs6 f21 pr5b 2 c g22 pr5a 2 t g24 pr4b 2 c g23 pr4a 2 t c26 pr3b 2 c c25 pr3a 2 t e23 pr2b 2 c vref1_2 d23 pr2a 2 t vref2_2 gnd gnd02 gnd gnd01 a24 pt57b 1 c a23 pt57a 1 t e18 pt56b 1 c d19 pt56a 1 t f19 pt55b 1 c b22 pt55a 1 t g19 pt54b 1 c b21 pt54a 1 t tdqs54 d18 pt53b 1 c gnd gnd01 c18 pt53a 1 t f18 pt52b 1 c a22 pt52a 1 t g18 pt51b 1 c lfecp20/lfec20 logic signal connections: 672 fpbga (cont.) ball number ball function bank lvds dual function 4-45 pinout information lattice semiconductor latticeecp/ec family data sheet a21 pt51a 1 t e17 pt50b 1 c b17 pt50a 1 t c17 pt49b 1 c gnd gnd01 d17 pt49a 1 t f17 pt48b 1 c e20 pt48a 1 t g17 pt47b 1 c b20 pt47a 1 t e16 pt46b 1 c a20 pt46a 1 t tdqs46 a19 pt45b 1 c gnd gnd01 b19 pt45a 1 t d16 pt44b 1 c c16 pt44a 1 t f16 pt43b 1 c a18 pt43a 1 t g16 pt42b 1 c b18 pt42a 1 t a17 pt41b 1 c gnd gnd01 a16 pt41a 1 t d15 pt40b 1 c b16 pt40a 1 t e15 pt39b 1 c c15 pt39a 1 t f15 pt38b 1 c g15 pt38a 1 t tdqs38 b15 pt37b 1 c gnd gnd01 a15 pt37a 1 t e14 pt36b 1 c g14 pt36a 1 t d14 pt35b 1 c vref2_1 e13 pt35a 1 t vref1_1 f14 pt34b 1 c c14 pt34a 1 t b14 pt33b 0 c pclkc0_0 gnd gnd01 a14 pt33a 0 t pclkt0_0 d13 pt32b 0 c vref1_0 c13 pt32a 0 t vref2_0 lfecp20/lfec20 logic signal connections: 672 fpbga (cont.) ball number ball function bank lvds dual function 4-46 pinout information lattice semiconductor latticeecp/ec family data sheet a13 pt31b 0 c b13 pt31a 0 t f13 pt30b 0 c f12 pt30a 0 t tdqs30 a12 pt29b 0 c gnd gnd00 b12 pt29a 0 t a11 pt28b 0 c b11 pt28a 0 t d12 pt27b 0 c c12 pt27a 0 t b10 pt26b 0 c a10 pt26a 0 t g12 pt25b 0 c gnd gnd00 a9 pt25a 0 t e12 pt24b 0 c b9 pt24a 0 t f11 pt23b 0 c a8 pt23a 0 t d11 pt22b 0 c c11 pt22a 0 t tdqs22 b8 pt21b 0 c gnd gnd00 b7 pt21a 0 t e11 pt20b 0 c a7 pt20a 0 t g11 pt19b 0 c c7 pt19a 0 t g10 pt18b 0 c c6 pt18a 0 t c10 pt17b 0 c gnd gnd00 d10 pt17a 0 t f10 pt16b 0 c a6 pt16a 0 t e10 pt15b 0 c c9 pt15a 0 t g9 pt14b 0 c d9 pt14a 0 t tdqs14 a5 pt13b 0 c gnd gnd00 a4 pt13a 0 t f9 pt12b 0 c lfecp20/lfec20 logic signal connections: 672 fpbga (cont.) ball number ball function bank lvds dual function 4-47 pinout information lattice semiconductor latticeecp/ec family data sheet b6 pt12a 0 t e9 pt11b 0 c c8 pt11a 0 t g8 pt10b 0 c b5 pt10a 0 t a3 pt9b 0 c gnd gnd00 a2 pt9a 0 t f8 pt8b 0 c b4 pt8a 0 t e8 pt7b 0 c b3 pt7a 0 t d8 pt6b 0 c g7 pt6a 0 t tdqs6 c4 pt5b 0 c c5 pt5a 0 t e7 pt4b 0 c d4 pt4a 0 t f7 pt3b 0 c d6 pt3a 0 t d7 pt2b 0 c e6 pt2a 0 t gnd gnd00 lfecp20/lfec20 logic signal connections: 672 fpbga (cont.) ball number ball function bank lvds dual function www.latticesemi.com 5-1 order info_01.1 october 2004 preliminary data sheet ? 2004 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci t cations and information herein are subject to change without notice. pa rt number description ordering information note: latticeecp/ec devices are dual marked. for example, the commercial speed grade lfec20e-4f484c is also marked with industrial grade -3i (lfec20e-3f484i). the commercial grade is one speed grade faster than the associated dual mark industrial grade. the slowest commercial speed grade does not have industrial markings. the markings appear as follows: latticeec commercial pa rt number i/os grade package pins temp. luts lfec1e-3q208c 112 -3 pqfp 208 com 1.5k lfec1e-4q208c 112 -4 pqfp 208 com 1.5k lfec1e-5q208c 112 -5 pqfp 208 com 1.5k lfec1e-3t144c 97 -3 tqfp 144 com 1.5k lfec1e-4t144c 97 -4 tqfp 144 com 1.5k lfec1e-5t144c 97 -5 tqfp 144 com 1.5k lfec1e-3t100c 67 -3 tqfp 100 com 1.5k lfxxx xx x ? x xxxx x grade c = commercial i = industrial logic capacity 1* = 1.5k luts 3* = 3k luts 6 = 6k luts 10 = 10k luts 15 = 15k luts 20 = 20k luts 33 = 33k luts 40 = 40k luts *not available in the latticeecp family. supply voltage e = 1.2v speed 3 = slowest 4 5 = fastest package t100 = 100-pin tqfp* t144 = 144-pin tqfp q208 = 208-pin pqfp f256 = 256-ball fpbga f484 = 484-ball fpbga f672 = 672-ball fpbga f900 = 900-ball fpbga device family lattice ec (fpga) lattice ecp (ec fpga + dsp blocks) lfec20c- 4f484c-3i datecode ec latticeecp/ec family data sheet ordering information 5-2 ordering information lattice semiconductor latticeecp/ec family data sheet lfec1e-4t100c 67 -4 tqfp 100 com 1.5k lfec1e-5t100c 67 -5 tqfp 100 com 1.5k pa rt number i/os grade package pins temp. luts lfec3e-3f256c 160 -3 fpbga 256 com 3.1k lfec3e-4f256c 160 -4 fpbga 256 com 3.1k lfec3e-5f256c 160 -5 fpbga 256 com 3.1k lfec3e-3q208c 145 -3 pqfp 208 com 3.1k lfec3e-4q208c 145 -4 pqfp 208 com 3.1k lfec3e-5q208c 145 -5 pqfp 208 com 3.1k lfec3e-3t144c 97 -3 tqfp 144 com 3.1k lfec3e-4t144c 97 -4 tqfp 144 com 3.1k lfec3e-5t144c 97 -5 tqfp 144 com 3.1k lfec3e-3t100c 67 -3 tqfp 100 com 3.1k lfec3e-4t100c 67 -4 tqfp 100 com 3.1k lfec3e-5t100c 67 -5 tqfp 100 com 3.1k pa rt number i/os grade package pins temp. luts lfec6e-3f484c 224 -3 fpbga 484 com 6.1k lfec6e-4f484c 224 -4 fpbga 484 com 6.1k lfec6e-5f484c 224 -5 fpbga 484 com 6.1k lfec6e-3f256c 195 -3 fpbga 256 com 6.1k lfec6e-4f256c 195 -4 fpbga 256 com 6.1k lfec6e-5f256c 195 -5 fpbga 256 com 6.1k lfec6e-3q208c 147 -3 pqfp 208 com 6.1k lfec6e-4q208c 147 -4 pqfp 208 com 6.1k lfec6e-5q208c 147 -5 pqfp 208 com 6.1k lfec6e-3t144c 97 -3 tqfp 144 com 6.1k lfec6e-4t144c 97 -4 tqfp 144 com 6.1k lfec6e-5t144c 97 -5 tqfp 144 com 6.1k pa rt number i/os grade package pins temp. luts lfec10e-3f484c 288 -3 fpbga 484 com 10.2k lfec10e-4f484c 288 -4 fpbga 484 com 10.2k lfec10e-5f484c 288 -5 fpbga 484 com 10.2k lfec10e-3f256c 195 -3 fpbga 256 com 10.2k lfec10e-4f256c 195 -4 fpbga 256 com 10.2k lfec10e-5f256c 195 -5 fpbga 256 com 10.2k lfec10e-3q208c 147 -3 pqfp 208 com 10.2k lfec10e-4q208c 147 -4 pqfp 208 com 10.2k lfec10e-5q208c 147 -5 pqfp 208 com 10.2k latticeec commercial (continued) pa rt number i/os grade package pins temp. luts 5-3 ordering information lattice semiconductor latticeecp/ec family data sheet lfec15e-3f484c 352 -3 fpbga 484 com 15.3k lfec15e-4f484c 352 -4 fpbga 484 com 15.3k lfec15e-5f484c 352 -5 fpbga 484 com 15.3k lfec15e-3f256c 195 -3 fpbga 256 com 15.3k lfec15e-4f256c 195 -4 fpbga 256 com 15.3k lfec15e-5f256c 195 -5 fpbga 256 com 15.3k pa rt number i/os grade package pins temp. luts lfec20e-3f672c 400 -3 fpbga 672 com 19.7k lfec20e-4f672c 400 -4 fpbga 672 com 19.7k lfec20e-5f672c 400 -5 fpbga 672 com 19.7k lfec20e-3f484c 360 -3 fpbga 484 com 19.7k lfec20e-4f484c 360 -4 fpbga 484 com 19.7k lfec20e-5f484c 360 -5 fpbga 484 com 19.7k pa rt number i/os grade package pins temp. luts lfec33e-3f672c 496 -3 fpbga 672 com 32.8k lfec33e-4f672c 496 -4 fpbga 672 com 32.8k lfec33e-4f672c 496 -5 fpbga 672 com 32.8k lfec33e-3f484c 360 -3 fpbga 484 com 32.8k lfec33e-4f484c 360 -4 fpbga 484 com 32.8k lfec33e-4f484c 360 -5 fpbga 484 com 32.8k pa rt number i/os grade package pins temp. luts lfec40e-3f900c 576 -3 fpbga 900 com 40.9k lfec40e-4f900c 576 -4 fpbga 900 com 40.9k lfec40e-5f900c 576 -5 fpbga 900 com 40.9k lfec40e-3f672c 496 -3 fpbga 672 com 40.9k lfec40e-4f672c 496 -4 fpbga 672 com 40.9k lfec40e-5f672c 496 -5 fpbga 672 com 40.9k latticeecp commercial pa rt number i/os grade package pins temp. luts lfecp6e-3f484c 224 -3 fpbga 484 com 6.1k lfecp6e-4f484c 224 -4 fpbga 484 com 6.1k lfecp6e-5f484c 224 -5 fpbga 484 com 6.1k lfecp6e-3f256c 195 -3 fpbga 256 com 6.1k lfecp6e-4f256c 195 -4 fpbga 256 com 6.1k lfecp6e-5f256c 195 -5 fpbga 256 com 6.1k lfecp6e-3q208c 147 -3 pqfp 208 com 6.1k lfecp6e-4q208c 147 -4 pqfp 208 com 6.1k lfecp6e-5q208c 147 -5 pqfp 208 com 6.1k lfecp6e-3t144c 97 -3 tqfp 144 com 6.1k latticeec commercial (continued) pa rt number i/os grade package pins temp. luts 5-4 ordering information lattice semiconductor latticeecp/ec family data sheet lfecp6e-4t144c 97 -4 tqfp 144 com 6.1k lfecp6e-5t144c 97 -5 tqfp 144 com 6.1k pa rt number i/os grade package pins temp. luts lfecp10e-3f484c 288 -3 fpbga 484 com 10.2k lfecp10e-4f484c 288 -4 fpbga 484 com 10.2k lfecp10e-5f484c 288 -5 fpbga 484 com 10.2k lfecp10e-3f256c 195 -3 fpbga 256 com 10.2k lfecp10e-4f256c 195 -4 fpbga 256 com 10.2k lfecp10e-5f256c 195 -5 fpbga 256 com 10.2k lfecp10e-3q208c 147 -3 pqfp 208 com 10.2k lfecp10e-4q208c 147 -4 pqfp 208 com 10.2k lfecp10e-5q208c 147 -5 pqfp 208 com 10.2k pa rt number i/os grade package pins temp. luts lfecp15e-3f484c 352 -3 fpbga 484 com 15.3k lfecp15e-4f484c 352 -4 fpbga 484 com 15.3k lfecp15e-5f484c 352 -5 fpbga 484 com 15.3k lfecp15e-3f256c 195 -3 fpbga 256 com 15.3k lfecp15e-4f256c 195 -4 fpbga 256 com 15.3k lfecp15e-5f256c 195 -5 fpbga 256 com 15.3k pa rt number i/os grade package pins temp. luts lfecp20e-3f672c 400 -3 fpbga 672 com 19.7k lfecp20e-4f672c 400 -4 fpbga 672 com 19.7k lfecp20e-5f672c 400 -5 fpbga 672 com 19.7k lfecp20e-3f484c 360 -3 fpbga 484 com 19.7k lfecp20e-4f484c 360 -4 fpbga 484 com 19.7k lfecp20e-5f484c 360 -5 fpbga 484 com 19.7k pa rt number i/os grade package pins temp. luts lfecp33e-3f672c 496 -3 fpbga 672 com 32.8k lfecp33e-4f672c 496 -4 fpbga 672 com 32.8k lfecp33e-4f672c 496 -5 fpbga 672 com 32.8k lfecp33e-3f484c 360 -3 fpbga 484 com 32.8k lfecp33e-4f484c 360 -4 fpbga 484 com 32.8k lfecp33e-4f484c 360 -5 fpbga 484 com 32.8k pa rt number i/os grade package pins temp. luts lfecp40e-3f900c 576 -3 fpbga 900 com 40.9k lfecp40e-4f900c 576 -4 fpbga 900 com 40.9k lfecp40e-5f900c 576 -5 fpbga 900 com 40.9k lfecp40e-3f672c 496 -3 fpbga 672 com 40.9k latticeecp commercial (continued) pa rt number i/os grade package pins temp. luts 5-5 ordering information lattice semiconductor latticeecp/ec family data sheet lfecp40e-4f672c 496 -4 fpbga 672 com 40.9k lfecp40e-5f672c 496 -5 fpbga 672 com 40.9k latticeec industrial pa rt number i/os grade package pins temp. luts lfec1e-3q208i 112 -3 pqfp 208 ind 1.5k lfec1e-4q208i 112 -4 pqfp 208 ind 1.5k lfec1e-3t144i 97 -3 tqfp 144 ind 1.5k lfec1e-4t144i 97 -4 tqfp 144 ind 1.5k lfec1e-3t100i 67 -3 tqfp 100 ind 1.5k lfec1e-4t100i 67 -4 tqfp 100 ind 1.5k pa rt number i/os grade package pins temp. luts lfec3e-3f256i 160 -3 fpbga 256 ind 3.1k lfec3e-4f256i 160 -4 fpbga 256 ind 3.1k lfec3e-3q208i 145 -3 pqfp 208 ind 3.1k lfec3e-4q208i 145 -4 pqfp 208 ind 3.1k lfec3e-3t144i 97 -3 tqfp 144 ind 3.1k lfec3e-4t144i 97 -4 tqfp 144 ind 3.1k LFEC3E-3T100I 67 -3 tqfp 100 ind 3.1k lfec3e-4t100i 67 -4 tqfp 100 ind 3.1k pa rt number i/os grade package pins temp. luts lfec6e-3f484i 224 -3 fpbga 484 ind 6.1k lfec6e-4f484i 224 -4 fpbga 484 ind 6.1k lfec6e-3f256i 195 -3 fpbga 256 ind 6.1k lfec6e-4f256i 195 -4 fpbga 256 ind 6.1k lfec6e-3q208i 147 -3 pqfp 208 ind 6.1k lfec6e-4q208i 147 -4 pqfp 208 ind 6.1k lfec6e-3t144i 97 -3 tqfp 144 ind 6.1k lfec6e-4t144i 97 -4 tqfp 144 ind 6.1k pa rt number i/os grade package pins temp. luts lfec10e-3f484i 288 -3 fpbga 484 ind 10.2k lfec10e-4f484i 288 -4 fpbga 484 ind 10.2k lfec10e-3f256i 195 -3 fpbga 256 ind 10.2k lfec10e-4f256i 195 -4 fpbga 256 ind 10.2k lfec10e-3 p208i 147 -3 pqfp 208 ind 10.2k lfec10e-4 p208i 147 -4 pqfp 208 ind 10.2k pa rt number i/os grade package pins temp. luts lfec15e-3f484i 352 -3 fpbga 484 ind 15.3k lfec15e-4f484i 352 -4 fpbga 484 ind 15.3k latticeecp commercial (continued) pa rt number i/os grade package pins temp. luts 5-6 ordering information lattice semiconductor latticeecp/ec family data sheet lfec15e-3f256i 195 -3 fpbga 256 ind 15.3k lfec15e-4f256i 195 -4 fpbga 256 ind 15.3k pa rt number i/os grade package pins temp. luts lfec20e-3f672i 400 -3 fpbga 672 ind 19.7k lfec20e-4f672i 400 -4 fpbga 672 ind 19.7k lfec20e-3f484i 360 -3 fpbga 484 ind 19.7k lfec20e-4f484i 360 -4 fpbga 484 ind 19.7k pa rt number i/os grade package pins temp. luts lfec33-3f672i 496 -3 fpbga 672 ind 32.8 lfec33-4f672i 496 -4 fpbga 672 ind 32.8 lfec33-3f484i 360 -3 fpbga 484 ind 32.8 lfec33-4f484i 360 -4 fpbga 484 ind 32.8 pa rt number i/os grade package pins temp. luts lfec40e-3f900i 576 -3 fpbga 900 ind 40.9k lfec40e-4f900i 576 -4 fpbga 900 ind 40.9k lfec40e-3f672i 496 -3 fpbga 672 ind 40.9k lfec40e-4f672i 496 -4 fpbga 672 ind 40.9k latticeecp industrial pa rt number i/os grade package pins temp. luts lfecp6e-3f484i 224 -3 fpbga 484 ind 6.1k lfecp6e-4f484i 224 -4 fpbga 484 ind 6.1k lfecp6e-3f256i 195 -3 fpbga 256 ind 6.1k lfecp6e-4f256i 195 -4 fpbga 256 ind 6.1k lfecp6e-3q208i 147 -3 pqfp 208 ind 6.1k lfecp6e-4q208i 147 -4 pqfp 208 ind 6.1k lfecp6e-3t144i 97 -3 tqfp 144 ind 6.1k lfecp6e-4t144i 97 -4 tqfp 144 ind 6.1k pa rt number i/os grade package pins temp. luts lfecp10e-3f484i 288 -3 fpbga 484 ind 10.2k lfecp10e-4f484i 288 -4 fpbga 484 ind 10.2k lfecp10e-3f256i 195 -3 fpbga 256 ind 10.2k lfecp10e-4f256i 195 -4 fpbga 256 ind 10.2k lfecp10e-3q208i 147 -3 pqfp 208 ind 10.2k lfecp10e-4q208i 147 -4 pqfp 208 ind 10.2k latticeec industrial (continued) pa rt number i/os grade package pins temp. luts 5-7 ordering information lattice semiconductor latticeecp/ec family data sheet pa rt number i/os grade package pins temp. luts lfecp15e-3f484i 352 -3 fpbga 484 ind 15.3k lfecp15e-4f484i 352 -4 fpbga 484 ind 15.3k lfecp15e-3f256i 195 -3 fpbga 256 ind 15.3k lfecp15e-4f256i 195 -4 fpbga 256 ind 15.3k pa rt number i/os grade package pins temp. luts lfecp20e-3f672i 400 -3 fpbga 672 ind 19.7k lfecp20e-4f672i 400 -4 fpbga 672 ind 19.7k lfecp20e-3f484i 360 -3 fpbga 484 ind 19.7k lfecp20e-4f484i 360 -4 fpbga 484 ind 19.7k pa rt number i/os grade package pins temp. luts lfecp33-3f672i 496 -3 fpbga 672 ind 32.8k lfecp33-4f672i 496 -4 fpbga 672 ind 32.8k lfecp33-3f484i 360 -3 fpbga 484 ind 32.8k lfecp33-4f484i 360 -4 fpbga 484 ind 32.8k pa rt number i/os grade package pins temp. luts lfecp40e-3f900i 576 -3 fpbga 900 ind 40.9k lfecp40e-4f900i 576 -4 fpbga 900 ind 40.9k lfecp40e-3f672i 496 -3 fpbga 672 ind 40.9k lfecp40e-4f672i 496 -4 fpbga 672 ind 40.9k latticeecp industrial (continued) october 2004 preliminary data sheet ? 2004 lattice semiconductor corp. all lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www .latticesemi.com/legal. all other brand or product names are trademarks or registered trademarks of their respective holders. the speci t cations and information herein are subject to change without notice. www.latticesemi.com 6-1 further info_01.1 for further information a variety of technical notes for the latticeecp/ec family are available on the lattice web site at www .latticesemi.com . ? latticeecp/ec sysio usage guide (tn1056) ? isptracy internal logic analyzer guide (tn1054) ? latticeecp/ec sysclock pll design and usage guide (tn1049) ? memory usage guide for latticeecp/ec devices (tn1051) ? latticeecp/ec ddr usage guide (tn1050) ? estimating power using power calculator for latticeecp/ec devices (tn1052) ? sysdsp/mac usage guide (tn1057) ? latticeecp/ec sysconfig usage guide (tn1053) ? ieee 1149.1 boundary scan testability in lattice devices f or further information on interface standards refer to the following web sites: ? jedec standards (lvttl, lvcmos, sstl, hstl): www .jedec.org ? pci: ww .pcisig.com latticeecp/ec family data sheet supplemental information |
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